• mirc/hash tables
  ...ating over a large number of hash table entries to find the item needed is CPU intensive and mIRC might start to feel unresponsive.
  30 KB (5,149 words) - 01:46, 30 November 2018
• mips/mips32 instruction set
  * CPU Instructions
  18 KB (2,445 words) - 08:24, 9 November 2019
• mips/coprocessor 0
  | [[Config register - MIPS|Config]] || 16 || rowspan="4" | CPU setup
  3 KB (384 words) - 10:11, 19 February 2018
• mirc/component object model
  === Dispatching example - CPU info === ;get some cool information about the CPU here
  27 KB (3,608 words) - 11:41, 25 October 2018
• intel/mcs-4/4004
  ...ly available [[microprocessor]]. The 4004 was a [[4-bit architecture|4-bit CPU]], designed for use in the [[Busicom]] 141-PF printing calculator<ref>[http
  5 KB (748 words) - 21:37, 21 November 2021
• rockwell international/pps-4/11660
  | image = Rockwell PPS4 11660 CPU.jpg ...It's full compatible with all the original {{rockwell|pps-4/10660|PPS-4}} CPU and all the other parts.
  2 KB (240 words) - 16:32, 13 December 2017
• hitachi/hmcs-4
  | arch = 4-bit ...ROM]] chip, a [[RAM]] chip, [[shift register]], and a [[4-bit architecture|4-bit]] [[microprocessor]]. The chipset was first produced first quarter of 1975.
  2 KB (266 words) - 00:54, 19 May 2016
• microprocessors used in spacecrafts
  ...10, its CPU was also a custom-designed [[transistor-transistor logic|TTL]] CPU. ...[[Voyager Flight Data System|Voyager's data computer]], which was a custom 4-bit CMOS microprocessor.
  11 KB (1,334 words) - 18:26, 10 May 2019
• intel/3000
  | caption = Intel D3002, CPU of the 3000 series | {{\|3002}} || CPU
  3 KB (308 words) - 05:03, 18 February 2020
• mirc/optimization
  ...iterations per chunk (bearing in mind that it may run on PCs of different CPU powers). Clearly you want to keep the iterations small enough that mIRC con
  13 KB (2,047 words) - 07:44, 23 February 2023
• intel/mcs-4
  | arch = 4-bit word, 8-bit instruction, BCD-oriented ...re chipset was made of four individual chips, including the [[/4004|4004]] CPU which became the first commercial microprocessor. MCS-4 was completed by Ma
  4 KB (433 words) - 22:40, 27 June 2019
• intel/core i7/i7-5775c
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (460 words) - 15:03, 24 March 2019
• microcontroller
  ...em to function as a single computer on a chip. This usually includes the [[CPU]], [[program memory|program]] and [[data memory]], [[programmable I/O|progr
  2 KB (344 words) - 15:51, 21 March 2024
• rockwell international/pps-4
  | arch = 4-bit words, 8-bit instruction The '''PPS-4''' (Parallel Processing System - 4-bit word) was a [[microprocessor family|family]] of {{arch|4}} [[microprocessor
  3 KB (359 words) - 17:26, 19 May 2016
• nec/μcom-43/μpd557l
  ...1980 Catalog, "μCOM-4: 4-Bit Single Chip Microcomputer Family, μCOM-43SL CPU μPD557L", 104, 125-126 pp. *NEC Microcomputers, Inc., 1981 Catalog, "μCOM-4: 4-Bit Single Chip Microcomputer Family, μPD557L μCOM-43SL", 155, 177-178 pp.
  2 KB (244 words) - 06:13, 1 August 2018
• rockwell international/pps-4-1
  | arch = 4-bit words, 8-bit instruction ...system (hence the "/1"). It's full compatible with all the original PPS-4 CPU and all the other parts.
  2 KB (219 words) - 01:00, 19 May 2016
• intel/atom
  ...power came from its simplicity, being an [[in-order]] dual-issue pipelined CPU. All Bonnell-based processors were manufactured on Intel's [[45 nm process] Silverthorne chips have an incredibly simple design featuring only the CPU itself on-die. The [[southbridge]] and [[northbridge]] are integrated on a
  17 KB (2,292 words) - 09:32, 16 July 2019
• fairchild/f8
  | caption = The F3850 [[CPU]] component | {{\|3850}} || [[CPU]]
  2 KB (172 words) - 17:18, 12 December 2016
• hitachi/6309/a memo on the secret features of 6309
  The CPU 6309 by HITACHI has secret features which is not written in with instructions of the Hitachi 6301 CPU. Read the manual of the 6301
  31 KB (2,938 words) - 14:54, 17 March 2016
• intel/mcs-8
  | caption = CPU, {{\|8008-1}} higher speed variant ...[Intel]]. Introduced on April, [[1972]], the MCS-8 featured the {{\|8008}} CPU.
  3 KB (382 words) - 17:58, 19 May 2016
• intel/mcs-80
  | caption = {{\|8080}}, the CPU of the MCS-80 system ...y [[Intel]]. Introduced on April, 1974, the MCS-80 featured the {{\|8080}} CPU, the forefather of all modern [[x86]]-based microprocessors.
  4 KB (406 words) - 16:10, 26 January 2019
• 32 nm lithography process
  | process 1 name = P1268 (CPU) / P1269 (SoC)
  10 KB (1,090 words) - 19:14, 8 July 2021
• 14 nm lithography process
  | process 1 name = P1272 (CPU) / P1273 (SoC) ...or performance and high frequency (e.g., high-switching circuitry in the [[CPU]]) whereas short cells are optimized for density (e.g., GPU shader arrays).
  17 KB (2,243 words) - 19:32, 25 May 2023
• 45 nm lithography process
  | colspan="2" | P1266 (CPU) / P1266.8 (SoC) / P1269 (SoC) || colspan="2" | CS-300 || colspan="2" | ||
  5 KB (602 words) - 05:51, 20 July 2018
• intel/microarchitectures/bonnell
  |atype=CPU ...tel turned to higher integration, moving [[integrated graphics|Graphics]], CPU core, Video Acceleration, [[Display Controller]], and [[Memory Controller]]
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  | atype = CPU <tr><th colspan="8">CPU</th><th colspan="3">IGP</th></tr>
  7 KB (872 words) - 19:42, 30 November 2017
• intel/microarchitectures/silvermont
  | atype = CPU
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/microarchitectures/airmont
  | atype = CPU
  5 KB (568 words) - 19:40, 30 November 2017
• intel/microarchitectures/goldmont
  |atype=CPU
  7 KB (956 words) - 23:05, 23 March 2020
• intel/pentium (2009)
  <tr><th colspan="8">CPU</th><th colspan="3">IGP</th></tr> ...ated the [[integrated graphics]] on this same die as the newly architected CPU, allowing for higher performance and lower power than previous generation.
  20 KB (2,661 words) - 00:45, 11 October 2017
• intel/celeron
  <tr><th colspan="8">CPU</th><th colspan="3">IGP</th></tr>
  25 KB (3,201 words) - 03:13, 22 September 2018
• intel/xeon d
  All models are a single-chip solution, meaning both the [[CPU]] [[die]] and the [[chipset]] die are packaged together on the same substra All models are a single-chip solution, meaning both the [[CPU]] [[die]] and the [[chipset]] die are packaged together on the same substra
  13 KB (1,784 words) - 08:04, 6 April 2019
• intel/microarchitectures/broadwell (client)
  |atype=CPU ...l]] [[instance of::microprocessor]] [[microarchitecture::Broadwell]] [[max cpu count::1]]
  14 KB (1,891 words) - 14:37, 6 January 2022
• intel/microarchitectures/haswell (client)
  |atype=CPU ==== CPU changes ====
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/ivy bridge (client)
  | atype = CPU * 4 CPU cores
  5 KB (689 words) - 13:44, 2 May 2020
• intel/microarchitectures/sandy bridge (client)
  |atype=CPU ...diagram from Intel. The master design incorporates the [[quad-core|four]] CPU [[physical cores|cores]], the [[GPU]] with 12 execution units, the 8 MiB sh
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/westmere (client)
  | atype = CPU ...l]] [[instance of::microprocessor]] [[microarchitecture::Westmere ]] [[max cpu count::1]]
  10 KB (1,258 words) - 21:07, 9 March 2018
• intel/microarchitectures/nehalem (client)
  | atype = CPU
  4 KB (459 words) - 21:44, 26 December 2023
• intel/microarchitectures/p6
  | atype = CPU
  3 KB (325 words) - 21:34, 22 February 2020
• intel/microarchitectures/skylake (client)
  |atype=CPU **** Limits motherboard trace design to 7 inches max from the CPU to chipset (down from 8)
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  |atype=CPU ...her via Intel's standard [[DMI 3.0]] bus interface which utilizes 4 of the CPU's 20 [[PCIe]] 3.0 lanes (having a transfer rate of 8 GT/s per lane). Only {
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/cannon lake
  |atype=CPU * 2 CPU cores + 40 GPU EUs
  7 KB (887 words) - 12:53, 5 August 2019
• intel/microarchitectures/ice lake (client)
  |atype=CPU ...in-and-light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|G
  23 KB (3,613 words) - 12:31, 20 June 2021
• intel/microarchitectures/tiger lake
  |atype=CPU
  3 KB (406 words) - 10:46, 19 July 2023
• intel/core i7ee/i7-6950x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (564 words) - 14:29, 24 March 2019
• 10 nm lithography process
  | process 1 name = P1274 (CPU) / P1275 (SoC) ** CPU
  14 KB (1,903 words) - 06:52, 17 February 2023
• nvidia
  == CPU Families == '''CPU:'''
  3 KB (261 words) - 16:48, 20 March 2024
• intel/80486/486dx-33
  File:Intel i486 DX33 CPU SX 419.jpg|A80486DX-33, S-Spec SX419
  3 KB (321 words) - 02:59, 18 December 2017
• intel/80486/486dx-50
  | image = CPU Intel 80486DX-50.JPG File:Intel i486 DX 50 CPU.jpg|A80486DX-50, S-Spec SX710
  3 KB (265 words) - 16:13, 13 December 2017
• intel/80486/486dx2-50
  | image = Ic-photo-Intel--SB80486DX2-50--(486-CPU).JPG
  3 KB (345 words) - 16:13, 13 December 2017
• intel/80486/486dx2-66
  File:Intel i486 DX2 66 CPU SX750.jpg|A80486DX2-66, S-Spec SX750 File:Intel i486 DX2 66 CPU SX955.jpg|A80486DX2-66, S-Spec SX955
  4 KB (372 words) - 06:28, 15 February 2024
• intel/80486/486dx4-75
  | image = Ic-photo-Intel--FC80486DX4-75--(486-CPU).png
  3 KB (354 words) - 16:13, 13 December 2017
• intel/80486/486dx4-100
  Ic-photo-Intel--A80486DX4100-(486DX4-CPU).png|A80486DX4100, S-Spec SK096
  4 KB (414 words) - 16:13, 13 December 2017
• intel/80486/486sx-33
  File:Ic-photo-Intel--SB80486SX-33--(486-CPU).JPG|SB80486SX-33
  4 KB (345 words) - 16:14, 13 December 2017
• amd/am486/am486dx-40
  | image = Ic-photo-AMD--Am486DX-40-(A80486DX-40)-(486-CPU).jpg File:AMD Am486 DX 40 CPU E.jpg
  3 KB (270 words) - 15:18, 13 December 2017
• amd/am486/am486dx2-80
  This is the fastest regular 486-type CPU that has also been available as a native 5 Volt part.
  1 KB (209 words) - 21:53, 7 February 2024
• amd/am486/am486dx2-66
  File:AMD Am486 DX2 66 CPU E6.jpg| File:AMD Am486 DX2 66 CPU D.jpg
  3 KB (286 words) - 15:18, 13 December 2017
• amd/am486/am486dx4-100nv8t
  | image = Ic-photo-AMD--A80486DX4-100NV8T-(486-CPU).png File:AMD Am486 DX4 100 NV8T CPU.jpg|
  3 KB (348 words) - 15:19, 13 December 2017
• amd/am5x86
  * [[:File:CPU Thermal Management (Am486, Am5x86, K5) (August 1995).pdf|CPU Thermal Management]]; Publication #18448 Revision D/0; August 1995.
  7 KB (1,043 words) - 16:50, 14 June 2020
• amd/am5x86/am486dx5-133w16bgc
  | image = Ic-photo-AMD--Am5x86-P75-(Am486DX5-133W16BGC)-(486-CPU).jpg File:Ic-photo-AMD--Am5x86-P75-(Am486DX5-133W16BGC)-(486-CPU).jpg|1997, Week 46
  3 KB (358 words) - 15:19, 13 December 2017
• amd/am5x86/am486dx5-133v16bhc
  File:Ic-photo-AMD--AM486DX5-133V16BHC--(Am5x86-P75)--(486-CPU).JPG
  3 KB (342 words) - 15:19, 13 December 2017
• amd/am5x86/amd-x5-133adw
  File:Ic-photo-AMD--AMD-X5-133ADW-(Am5x86-P75)-(586-CPU).png|From 1996 Week 10
  3 KB (336 words) - 15:19, 13 December 2017
• amd/am286/n80l286-16
  | image = Ic-photo-AMD--N80L286-16 S-(286-CPU).png
  3 KB (281 words) - 15:18, 13 December 2017
• amd/am286/r80286-10
  | image = Ic-photo-AMD--R80286-10 S-(286-CPU).png
  3 KB (296 words) - 15:18, 13 December 2017
• amd/am286zx-lx/ng286lx-12
  * CPU shutdown mode; System shutdown mode
  3 KB (339 words) - 15:18, 13 December 2017
• amd/am286zx-lx/ng286lx-16
  * CPU shutdown mode; System shutdown mode
  3 KB (339 words) - 15:18, 13 December 2017
• amd/am186/n80c186
  | image = Ic-photo-AMD--N80C186-(186-CPU).png
  3 KB (280 words) - 04:32, 22 October 2019
• amd/am186/n80c186-16
  | image = Ic-photo-AMD--N80C186-16-(186-CPU).png
  3 KB (286 words) - 15:17, 13 December 2017
• amd/am186/r80186-6
  | image = Ic-photo-AMD--R80186-6 B4-(186-CPU).png
  3 KB (250 words) - 15:17, 13 December 2017
• intel/xeon e7
  |?max cpu count
  4 KB (482 words) - 05:08, 18 February 2020
• rapport/kilocore
  ...e 1025 model is the same as the 1024 model with an additional IBM Power PC CPU core incorporated as well for general-purpose tasks. These two models appea
  2 KB (254 words) - 03:53, 25 June 2016
• ambric/am2000/am2045
  *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU
  3 KB (367 words) - 15:16, 13 December 2017
• ambric/am2000/am2035
  *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU
  3 KB (280 words) - 15:16, 13 December 2017
• ambric/am2000/am2024
  *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU
  3 KB (280 words) - 15:16, 13 December 2017
• ambric/am2000/am2012
  *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU
  3 KB (280 words) - 15:16, 13 December 2017
• ambric/am2000/am2045b
  *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU
  3 KB (344 words) - 15:16, 13 December 2017
• ambric/am2000/am2029
  *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU
  3 KB (256 words) - 15:16, 13 December 2017
• ambric/am2000/am2016
  *** 2x SRD {{arch|32}} CPU *** 2x RD {{arch|32}} CPU
  3 KB (256 words) - 15:16, 13 December 2017
• intrinsity/fastmath
  | arch = 32-bit vector/matrix math processor + RISC cpu ...as a family of matrix and vector math processors with an on-die [[RISC]] [[CPU]]s introduced by [[Intrinsity]]. The chips were developed using Intrinsity'
  4 KB (464 words) - 17:41, 3 July 2016
• intrinsity/fastmath/fastmath-1.5
  ...erating at 1.5 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
  3 KB (317 words) - 16:30, 13 December 2017
• intrinsity/fastmath/fastmath-2
  ...operating at 2 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
  3 KB (318 words) - 16:30, 13 December 2017
• intrinsity/fastmath/fastmath-lp
  ...operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-powe
  3 KB (334 words) - 16:31, 13 December 2017
• intrinsity/fastmath/fastmath-3
  ...operating at 3 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
  3 KB (306 words) - 16:31, 13 December 2017
• amd/k5/amd-ssa-5-75abr
  File:Ic-photo-AMD--AMD-SSA 5-75ABR-(AMD5k86-P75-CPU).png
  3 KB (313 words) - 16:08, 13 December 2017
• amd/k5/amd-k5-pr100abq
  File:Ic-photo-AMD--AMD-K5-PR100ABQ-(K5-CPU).jpg
  3 KB (308 words) - 16:07, 13 December 2017
• amd/k6/amd-k6-166alr
  File:Ic-photo-AMD--AMD-K6-166ALR-(K6-CPU).jpg|166ALR, Week 35, 1997 File:Ic-photo-AMD--AMD-K6-166ALR-(K6-CPU).png|166ALR, Week 35, 1997
  3 KB (343 words) - 16:09, 13 December 2017
• intel/microarchitectures/coffee lake
  |atype=CPU The Coffee Lake system on a chip consists of a five major components: CPU [[physical core|cores]], [[last level cache|LLC]], Ring interconnect, {{int
  30 KB (4,192 words) - 13:48, 10 December 2023
• amd/k6-2/k6-2-333afr
  | image = Ic-photo-AMD--AMD-K6-2 333AFR-(K6-2-CPU).png
  3 KB (387 words) - 16:08, 13 December 2017
• amd/k6-2/k6-2-500afx
  | image = Ic-photo-AMD--AMD-K6-2 500AFX-(K6-2-CPU).png
  3 KB (353 words) - 16:08, 13 December 2017
• amd/k6-2/k6-2-380ack
  | image = Ic-photo-AMD--AMD-K6-2 380ACK--(K6-2 CPU).jpg
  3 KB (347 words) - 16:08, 13 December 2017
• processor performance rating (p-rating) specification
  ...ame pinout and bus interface, a single system can be used by replacing the CPU between tests. Section 3 lists the hardware components for the systems and
  11 KB (1,244 words) - 06:26, 8 July 2020
• amd/duron/d800aut1b
  | image = CPU AMD Duron 800.jpg
  4 KB (438 words) - 16:07, 13 December 2017
• amd/duron/d900aut1b
  | image = Ic-photo-AMD--D900AUT1B-(K7-Duron-CPU).png
  4 KB (437 words) - 16:07, 13 December 2017
• princeton/piton
  ...] core (+L1$), an L1.5 cache, L2 cache, a [[floating-point unit]] (FPU), a CPU Cache-Crossbar (CCX) arbiter, and three [[network on chip]] (NoC) routers.
  6 KB (731 words) - 15:41, 5 July 2018
• amd/microarchitectures/k6
  | atype = CPU
  4 KB (578 words) - 18:57, 22 May 2019
• amd/microarchitectures/k7
  |atype=CPU ...s by amd]] [[instance of::microprocessor]] [[microarchitecture::K7]] [[max cpu count::1]]
  6 KB (923 words) - 16:48, 3 March 2022
• amd/microarchitectures/k8
  |atype=CPU
  2 KB (261 words) - 01:06, 19 June 2023
• amd/microarchitectures/k9
  | atype = CPU
  2 KB (287 words) - 17:28, 1 December 2018
• amd/microarchitectures/k10
  |atype=CPU
  2 KB (261 words) - 16:24, 4 January 2022
• amd/microarchitectures/piledriver
  |atype=CPU
  2 KB (223 words) - 19:54, 14 July 2021
• amd/microarchitectures/zen
  |atype=CPU [[File:ryzen threadripper.png|right|thumb|First 16-core HEDT market CPU]]
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  |atype=CPU Zen 2 organizes CPU cores in a core complex (CCX). A CCX comprises four cores sharing a 16 MiB,
  57 KB (8,701 words) - 22:11, 9 October 2022
• amd/k6-iii/amd-k6-iii-333afr
  | image = Ic-photo-AMD--AMD-K6-III 333AFK-(K6-CPU).jpg
  3 KB (362 words) - 16:09, 13 December 2017
• intel/xeon e5
  ...tel]][[microprocessor family::Xeon E5]][[microarchitecture::Haswell]][[max cpu count::4]] |?max cpu count
  11 KB (1,395 words) - 08:36, 4 November 2020
• intel/xeon e5/e5-2690 v4
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (567 words) - 00:55, 29 April 2018
• amd/athlon 4
  File:AMD Athlon 4 (cpu and wafer).gif
  2 KB (199 words) - 17:44, 17 November 2016
• amd/am9080/am9080adc
  File:Ic-photo-AMD--AM9080ADC-(8080-CPU).png
  2 KB (241 words) - 15:20, 13 December 2017
• amd/am9080/am9080apcb
  | image = Ic-photo-AMD--AM9080APCB-(8080-CPU).png
  2 KB (229 words) - 15:20, 13 December 2017
• intel/hd graphics (ironlake)
  ...e are Intel's fifth generation integrated GPUs and first packaged GPU with CPU. <tr><th colspan="10">CPU</th><th colspan="3">IGP</th><th colspan="4">Features</th></tr>
  3 KB (378 words) - 03:16, 1 December 2016
• intel/cores/arrandale
  <tr><th colspan="10">CPU</th><th colspan="3">IGP</th><th colspan="4">Features</th></tr>
  4 KB (537 words) - 01:12, 28 August 2017
• arm holdings/microarchitectures/cortex-a53
  |atype=CPU * Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance
  6 KB (758 words) - 13:01, 6 March 2022
• mediatek/helio/mt6797
  The Helio X20 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applicat * Mair, Hugh T., et al. "4.3 A 20nm 2.5 GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance
  6 KB (713 words) - 21:16, 2 May 2021
• mediatek/helio/mt6797m
  The Helio X20 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applicat
  6 KB (617 words) - 02:35, 14 December 2019
• mediatek/helio/mt6797t
  The Helio X20 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applicat
  5 KB (581 words) - 14:25, 12 September 2019
• mediatek/helio/mt6797d
  The Helio X23 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applicat
  5 KB (574 words) - 04:36, 23 June 2019
• mediatek/helio/mt6797x
  The Helio X27 is identical to {{\\|Helio X20}} with higher CPU clocks speed and higher GPU clock speed. Additionally this model also suppo The Helio X27 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applicat
  5 KB (600 words) - 08:55, 12 October 2023
• mediatek/helio/mt6799
  The Helio X30 is designed is composed of 3 individual clusters of CPU cores depending on the level of performance required by the active applicat * Mair, Hugh, et al. "3.4 A 10nm FinFET 2.8 GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance."
  4 KB (549 words) - 16:22, 29 December 2018
• mediatek/helio/mt6755m
  ...(MT6755M) is identical to the regular {{\\|MT6755}} except for the GPU and CPU lower clock speeds.
  5 KB (614 words) - 09:40, 12 February 2020
• mediatek/helio/mt6755t
  ...ical to the {{\\|Helio P10}} with higher clock speeds for both the GPU and CPU.
  4 KB (552 words) - 23:18, 3 November 2019
• mediatek/helio/mt6757cd
  ...al to the {{\\|Helio P20}} apart from the higher clock speeds for both the CPU and GPU.
  4 KB (564 words) - 06:22, 30 March 2021
• cavium/microarchitectures/cnmips
  | atype = CPU <tr><th colspan="9">CPU</th><th colspan="3">Memory</th><th colspan="5">[[Hardware Accelerators]]</t
  7 KB (870 words) - 19:38, 23 June 2017
• cavium/octeon
  <tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="5">[[Hardware Accelerators]]</t <tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="5">[[Hardware Accelerators]]</t
  11 KB (1,489 words) - 09:25, 30 December 2020
• cavium/octeon plus
  <tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="4">[[Hardware Accelerators]]</t <tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="5">[[Hardware Accelerators]]</t
  6 KB (827 words) - 15:41, 29 December 2016
• mos technology
  ==CPU Families==
  2 KB (269 words) - 18:40, 31 August 2021
• intel/cores/kaby lake y
  ...solution - the [[chipset]] is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies
  4 KB (594 words) - 06:30, 6 April 2019
• intel/cores/kaby lake u
  ...ince they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Pack
  6 KB (820 words) - 14:10, 29 February 2020
• intel/microarchitectures/gen9.5
  ...SKU || EUs || CPU Stepping<ref group=devID>The CPU Stepping is the actual CPU design stepping.</ref> || GT Stepping<ref group=devID>The GT Stepping refer * Enhanced "14nm+" process (while CPU cores base frequency was increased, GPU speed remains unchanged)
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  ...SKU || EUs || CPU Stepping<ref group=devID>The CPU Stepping is the actual CPU design stepping.</ref> || GT Stepping<ref group=devID>The GT Stepping refer ...iB/CPU core || ~2MiB/CPU core || ~2MiB/CPU core || ~2MiB/CPU core || ~2MiB/CPU core
  33 KB (4,255 words) - 17:41, 1 November 2018
• ibm/microarchitectures/power9
  |atype=CPU ! Compiler !! CPU !! Arch-Favorable
  14 KB (1,905 words) - 23:38, 22 May 2020
• ibm/microarchitectures/power8
  | atype = CPU
  2 KB (217 words) - 15:30, 3 September 2017
• ibm/microarchitectures/power7+
  | atype = CPU
  2 KB (149 words) - 15:57, 3 September 2017
• ibm/microarchitectures/power7
  | atype = CPU
  2 KB (151 words) - 15:40, 3 September 2017
• ibm/microarchitectures/power6+
  | atype = CPU
  1 KB (136 words) - 06:09, 1 February 2017
• ibm/microarchitectures/power6
  | atype = CPU
  2 KB (147 words) - 15:35, 3 September 2017
• qualcomm/microarchitectures/falkor
  |atype=CPU
  6 KB (822 words) - 13:01, 19 May 2021
• intel/core i5/i5-7640x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  3 KB (517 words) - 10:12, 24 October 2018
• intel/core i7/i7-7740x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  3 KB (516 words) - 10:12, 24 October 2018
• phytium/microarchitectures/xiaomi
  |atype=CPU
  7 KB (940 words) - 00:12, 8 March 2021
• acorn/microarchitectures/arm1
  |atype=CPU
  12 KB (1,886 words) - 12:56, 14 January 2021
• amd/microarchitectures/zen 3
  |atype=CPU ...y amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::1]]
  15 KB (1,978 words) - 22:13, 6 April 2023
• 3 nm lithography process
  | process 1 name = P1278 (CPU), P1279? (SoC)
  5 KB (558 words) - 19:04, 29 December 2023
• intel/microarchitectures/merced
  | atype = CPU
  7 KB (978 words) - 21:16, 20 January 2021
• last level cache
  ...hat is usually shared by all the functional units on the chip (e.g. [[core|CPU cores]], [[IGP]], and [[DSP]]) ...d [[L2$]] and the GPU has its own L1, L2, and L3 cache. Therefore from the CPU core perspective, the LLC is effectively an L3 cache whereas from the GPU p
  859 bytes (143 words) - 14:16, 6 September 2017
• intel/xeon gold/5122
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (663 words) - 14:54, 12 January 2020
• intel/xeon gold/6126
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  7 KB (1,083 words) - 01:20, 29 December 2019
• intel/xeon gold/6126t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (723 words) - 01:20, 29 December 2019
• intel/xeon gold/6128
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (754 words) - 01:20, 29 December 2019
• intel/xeon gold/6130
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  9 KB (1,276 words) - 01:20, 29 December 2019
• intel/xeon gold/6130t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (733 words) - 01:20, 29 December 2019
• intel/xeon gold/6132
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (893 words) - 01:20, 29 December 2019
• intel/xeon gold/6134
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (778 words) - 01:20, 29 December 2019
• intel/xeon gold/6134m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (686 words) - 01:13, 24 May 2019
• intel/xeon gold/6136
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (891 words) - 01:20, 29 December 2019
• intel/xeon gold/6138
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (757 words) - 01:20, 29 December 2019
• intel/xeon gold/6138t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (765 words) - 01:45, 29 December 2019
• intel/xeon gold/6140
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  7 KB (1,070 words) - 01:45, 29 December 2019
• intel/xeon gold/6140m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (755 words) - 01:45, 29 December 2019
• intel/xeon gold/6142
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (912 words) - 01:45, 29 December 2019
• intel/xeon gold/6142m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (732 words) - 01:45, 29 December 2019
• intel/xeon gold/6148
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  8 KB (1,220 words) - 01:46, 29 December 2019
• intel/xeon gold/6150
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  9 KB (1,297 words) - 01:46, 29 December 2019
• intel/xeon gold/6152
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  7 KB (951 words) - 01:46, 29 December 2019
• intel/xeon gold/6154
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  9 KB (1,393 words) - 01:57, 29 December 2019
• intel/xeon platinum/8153
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  9 KB (1,264 words) - 02:37, 29 December 2019
• intel/xeon platinum/8156
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  9 KB (1,325 words) - 14:20, 8 May 2019
• intel/xeon platinum/8158
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  11 KB (1,616 words) - 14:20, 8 May 2019
• intel/xeon platinum/8160
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  9 KB (1,360 words) - 12:54, 24 August 2022
• intel/xeon platinum/8164
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  8 KB (1,160 words) - 02:38, 29 December 2019
• intel/xeon platinum/8168
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  9 KB (1,333 words) - 02:38, 29 December 2019
• intel/xeon platinum/8170
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  9 KB (1,357 words) - 02:38, 29 December 2019
• intel/xeon platinum/8176
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  11 KB (1,509 words) - 02:38, 29 December 2019
• intel/xeon platinum/8180
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  24 KB (3,386 words) - 02:38, 29 December 2019
• intel/process
  {{intel proc tech |year=2003 |name=P1262 (CPU)<br>P1263 (SoC, I/O) |mlayers=7 |node=90 nm {{intel proc tech |year=2005 |name=P1264 (CPU)<br>P1265 (SoC, I/O) |mlayers=8 |node=65 nm
  13 KB (1,998 words) - 03:56, 4 March 2022
• intel/cores/skylake sp
  ...by intel]] [[instance of::microprocessor]] [[core name::Skylake SP]] [[max cpu count::2]] ...by intel]] [[instance of::microprocessor]] [[core name::Skylake SP]] [[max cpu count::4]]
  7 KB (934 words) - 14:21, 10 June 2018
• amd/epyc
  <tr><th>7xxx</th><td>High-performance server CPU/SOC (Zen 1 to Zen 3)</td></tr> <tr><th>9xxx</th><td>High-performance server CPU/SOC (Zen 4)</td></tr>
  19 KB (2,580 words) - 02:46, 23 November 2022
• amd/cores/rome
  {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]] [[max cpu count::1]] {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]] [[max cpu count::>>1]]
  6 KB (828 words) - 16:47, 15 April 2020
• amd/cores/milan
  EPYC 7003 processors identify as members of {{amd|CPUID#Family 25 (19h)|AMD CPU Family 19h, Model 01h}} (engineering samples as Model 00h). ...he "Milan" CCD contains a single {{amd|Zen 3|l=arch}} CCX comprising eight CPU cores (the number of usable cores varies by <abbr title="Store Keeping Unit
  19 KB (2,734 words) - 01:26, 31 May 2021
• ibm/microarchitectures/power8+
  | atype = CPU
  1 KB (134 words) - 10:10, 26 September 2022
• intel/cores/coffee lake u
  ...chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP) along with the [[eDRAM]]. Communication b
  4 KB (553 words) - 23:05, 12 May 2020
• intel/core i7/i7-8550u
  * 4 CPU cores + 24 GPU EUs
  5 KB (787 words) - 02:57, 20 July 2023
• intel/core i7/i7-8650u
  * 4 CPU cores + 24 GPU EUs
  5 KB (787 words) - 16:38, 23 November 2018
• intel/xeon gold/5117
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (669 words) - 19:13, 3 August 2022
• intel/core i5/i5-8250u
  * 4 CPU cores + 24 GPU EUs
  5 KB (787 words) - 05:58, 9 October 2023
• arm holdings/microarchitectures/cortex-a55
  |atype=CPU
  4 KB (603 words) - 04:23, 27 April 2023
• arm holdings/microarchitectures/cortex-a75
  |atype=CPU
  2 KB (278 words) - 03:26, 6 May 2024
• dec/microarchitectures/strongarm
  |atype=CPU
  5 KB (738 words) - 13:49, 15 July 2018
• intel/core i7/i7-7800x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (601 words) - 17:13, 13 June 2019
• intel/core i7/i7-7820x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (613 words) - 07:01, 27 February 2019
• intel/core i9/i9-7900x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (617 words) - 10:13, 4 April 2019
• intel/core i9/i9-7920x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (614 words) - 10:17, 24 October 2018
• intel/core i9/i9-7940x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (606 words) - 14:34, 10 June 2020
• intel/core i9/i9-7960x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (608 words) - 15:46, 25 January 2019
• intel/cores/skylake y
  ...solution - the [[chipset]] is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies
  4 KB (571 words) - 06:30, 6 April 2019
• dec/microarchitectures/alpha 21264
  |atype=CPU
  2 KB (244 words) - 06:59, 13 June 2017
• compaq/microarchitectures/alpha 21364
  |atype=CPU
  2 KB (258 words) - 20:41, 14 June 2017
• compaq/microarchitectures/alpha 21464
  |atype=CPU
  2 KB (228 words) - 13:20, 31 March 2019
• dec/microarchitectures/alpha 21164
  |atype=CPU
  2 KB (206 words) - 11:52, 27 November 2020
• dec/microarchitectures/alpha 21064
  |atype=CPU
  4 KB (527 words) - 02:09, 4 August 2017
• amd/infinity fabric
  ...s architecture is utilized by [[AMD]]'s recent microarchitectures for both CPU (i.e., {{amd|Zen|l=arch}}) and graphics (e.g., {{amd|Vega|l=arch}}), and an ...=arch}}, the block diagram of the SDF is shown on the right. The two {{amd|CPU Complex|CCX's}} are directly connected to the SDF plane using the '''Cache-
  8 KB (1,271 words) - 21:50, 18 August 2020
• amd/ryzen threadripper/1900x
  {{see also|amd/frequency_behavior|l1=AMD's CPU Frequency Behavior}}
  4 KB (595 words) - 14:27, 19 December 2018
• amd/ryzen threadripper/1920x
  {{see also|amd/frequency_behavior|l1=AMD's CPU Frequency Behavior}}
  4 KB (616 words) - 23:43, 22 September 2019
• amd/ryzen threadripper/1950x
  {{see also|amd/frequency_behavior|l1=AMD's CPU Frequency Behavior}}
  4 KB (609 words) - 12:49, 5 August 2019
• acorn/microarchitectures/arm2
  |atype=CPU
  14 KB (2,093 words) - 04:42, 10 July 2018
• acorn/microarchitectures/arm3
  |atype=CPU
  7 KB (1,035 words) - 06:24, 21 November 2023
• amd/ryzen 7/pro 1700
  This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM).
  4 KB (600 words) - 23:55, 25 March 2023
• amd/ryzen 7/pro 1700x
  This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM).
  4 KB (604 words) - 23:55, 25 March 2023
• arm holdings/microarchitectures/arm6
  |atype=CPU
  11 KB (1,679 words) - 18:49, 18 May 2023
• intel/cores/skylake u
  ...ince they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Pack
  5 KB (743 words) - 08:07, 21 August 2017
• intel/xeon gold/5120
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  7 KB (1,079 words) - 23:48, 28 December 2019
• intel/xeon gold/5115
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (661 words) - 23:43, 28 December 2019
• intel/xeon gold/5118
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (776 words) - 23:43, 28 December 2019
• intel/xeon gold/6126f
  The 135 W of TDP for this microprocessor consists of 127 W for the CPU and 8 W for the fabric. {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (733 words) - 01:20, 29 December 2019
• intel/xeon gold/5120t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (711 words) - 23:48, 28 December 2019
• intel/xeon gold/6130f
  The 135 W of TDP for this microprocessor consists of 127 W for the CPU and 8 W for the fabric. {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (742 words) - 01:20, 29 December 2019
• intel/xeon gold/6142f
  The 160 W of TDP for this microprocessor consists of 152 W for the CPU and 8 W for the fabric. {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (746 words) - 01:45, 29 December 2019
• x86/avx-512
  ...isabled if power or thermal limits are reached instead of downclocking the CPU core which also affects uncritical instructions. If AVX-512 features are no ...lly zeros the elements in the destination where the corresponding bit in a 4-bit mask is set. The indices and the mask are constants in an immediate byte. B
  83 KB (13,667 words) - 15:45, 16 March 2023
• intel/xeon silver/4112
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  7 KB (993 words) - 12:16, 29 December 2019
• intel/xeon gold/5119t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (696 words) - 19:16, 3 August 2022
• intel/xeon gold/6144
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (863 words) - 01:45, 29 December 2019
• intel/xeon gold/6146
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  8 KB (1,123 words) - 01:45, 29 December 2019
• intel/xeon gold/6138f
  The 135 W of TDP for this microprocessor consists of 127 W for the CPU and 8 W for the fabric. {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (775 words) - 01:20, 29 December 2019
• intel/xeon gold/6148f
  The 160 W of TDP for this microprocessor consists of 152 W for the CPU and 8 W for the fabric. {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (775 words) - 01:45, 29 December 2019
• intel/xeon gold/5117f
  The 113 W of TDP for this microprocessor consists of 105 W for the CPU and 8 W for the fabric. {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (717 words) - 19:14, 3 August 2022
• ibm/microarchitectures/z990
  |atype=CPU
  987 bytes (125 words) - 01:48, 6 November 2017
• ibm/microarchitectures/z14
  |atype=CPU
  8 KB (1,204 words) - 14:02, 23 September 2019
• intel/microarchitectures/skylake (server)
  |atype=CPU ...imits motherboard trace design to 7 inches max from (down from 8) from the CPU to chipset
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/goldmont plus
  |atype=CPU
  9 KB (1,128 words) - 13:28, 17 July 2023
• intel/core i7/i7-8700k
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  7 KB (977 words) - 01:05, 22 July 2022
• intel/core i7/i7-8700
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (831 words) - 17:29, 11 February 2021
• intel/core i5/i5-8600k
  | Top 98% || 4.9 GHz || -2 || 1.387 V || || 97% || 4.9 GHz || -2 || CPU Vcore: 1.385 V | Top 84% || 5.0 GHz || -2 || 1.400 V || || 88% || 5.0 GHz || -2 || CPU Vcore: 1.400 V
  6 KB (907 words) - 09:45, 29 August 2018
• intel/core i5/i5-8400
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (832 words) - 03:34, 1 October 2020
• intel/core i5/i5-8350u
  * 4 CPU cores + 24 GPU EUs
  5 KB (784 words) - 16:39, 23 November 2018
• wikichip/stats/microarchitectures
  == CPU ==
  9 KB (1,178 words) - 21:51, 1 June 2018
• intel/cores/sandy bridge m
  ...architecture which incorporated both the IMC, integrated graphics, and the CPU [[physical core|cores]] onto the same monolithic die. All models communicat
  3 KB (489 words) - 15:57, 4 September 2017
• counter
  ...by the main clock -- to generate regular timing pulses that interrupt the CPU for pre-emptive multitasking.
  2 KB (303 words) - 00:30, 28 August 2017
• intel/cores/kaby lake r
  ...es which incorporated an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Pack
  5 KB (751 words) - 09:52, 11 February 2019
• intel/upgrade service
  ...change is semi-permanent and is associated with a motherboard and not the CPU. Activation is likely saved on the motherboard along with the [[BIOS]]. The ...tive [https://www.pcper.com/news/Processors/Intel-selling-scratch-software-CPU-upgrades noted] that for the Pentium part, it's only $15 to buy a Core i3 i
  4 KB (545 words) - 12:49, 18 July 2020
• intel/xeon w/w-2195
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (668 words) - 17:10, 14 May 2019
• intel/xeon w/w-2175
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (630 words) - 17:09, 14 May 2019
• intel/xeon w/w-2155
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (607 words) - 15:22, 3 July 2019
• intel/xeon w/w-2145
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (609 words) - 17:07, 14 May 2019
• intel/xeon w/w-2135
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (583 words) - 17:06, 14 May 2019
• intel/xeon w/w-2133
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (575 words) - 17:03, 14 May 2019
• intel/xeon w/w-2125
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (574 words) - 17:03, 14 May 2019
• intel/xeon w/w-2123
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (584 words) - 17:03, 14 May 2019
• ibm/microarchitectures/power5
  | atype = CPU
  2 KB (146 words) - 15:47, 3 September 2017
• ibm/microarchitectures/power4
  | atype = CPU
  1 KB (142 words) - 16:07, 3 September 2017
• hisilicon/kirin/970
  ...ng 50% less power and performing around 25 times faster than a traditional CPU for tasks such as photo recognition. The NPU is said to deliver 1.92 [[TFLO
  6 KB (824 words) - 17:25, 1 January 2022
• apple/ax/a11
  ...event on September 12 2017, the ''A11 Bionic'' features six {{arch|64}} [[CPU]] [[physical core|cores]]. Fabricated on [[TSMC]]'s [[10 nm process]], the
  4 KB (661 words) - 23:51, 3 January 2021
• microsoft/scorpio engine
  ...ollers]] and the CPUs and GPU. The bus maintains [[coherency]] between the CPU cores and the GPU. For the GPU, each of the 12 [[memory channel|channels]] ...essors such as typical [[CPU]]s and [[GPU]]s, when a core in the case of a CPU or a shader unit in the case of a GPU has a defect, it's common for manufac
  15 KB (2,390 words) - 02:54, 17 May 2023
• amd/microarchitectures/zen+
  |atype=CPU
  11 KB (1,613 words) - 08:39, 3 March 2024
• intel/microarchitectures/sapphire rapids
  |atype=CPU
  2 KB (251 words) - 00:26, 13 November 2022
• voltage regulator module
  ...re point ''A'' and convert it to the much lower operating voltage of the [[CPU]] or [[GPU]] at point ''B'' which is something like 1.2 V. ...reaches 12 V. The graph below depicts the voltage that would be fed to the CPU/GPU at point ''B'' if the high-side switch was to remain closed for a suffi
  18 KB (3,026 words) - 16:55, 19 January 2020
• nudt/matrix-2000
  ...ters. Each cluster consists of a router, a directory control unit (DCU), 4 CPU [[physical core|cores]] and a shared cache. Attached to each SuperNode are
  6 KB (894 words) - 07:26, 19 July 2019
• amd/cores/raven ridge
  ...ries of mainstream mobile and desktop APUs based on the {{amd|Zen|l=arch}} CPU and {{amd|Vega|l=arch}} GPU microarchitectures succeeding {{\\|Bristol Ridg
  3 KB (418 words) - 13:58, 17 March 2023
• zettascaler
  ZettaScalers use a host CPU (typically a {{intel|Xeon E5}}) which is then used to offload work to the {
  7 KB (857 words) - 20:39, 13 January 2018
• qualcomm/microarchitectures/saphira
  |atype=CPU
  1 KB (171 words) - 19:12, 11 October 2019
• intel/core i5/i5-8400t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (743 words) - 09:44, 29 August 2018
• intel/core i5/i5-8500
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (782 words) - 08:13, 5 February 2019
• intel/core i5/i5-8500t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (741 words) - 09:44, 29 August 2018
• intel/core i5/i5-9400
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (743 words) - 17:15, 26 May 2019
• intel/core i5/i5-9600k
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (719 words) - 16:20, 23 September 2021
• 2018
  * June 24: Fujitsu announces their {{fujitsu|Post-K|l=arch}} CPU prototype was complete
  5 KB (639 words) - 01:27, 30 December 2019
• intel/core i7/i7-8700t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (745 words) - 11:34, 15 April 2019
• intel/core i7/i7-9700k
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (806 words) - 16:31, 7 August 2023
• sun microsystems/ultrasparc/stp1030bga-143
  |image=Ic-photo-Sun--STP1030BGA-143--(Ultra SPARC-CPU).jpg
  1 KB (171 words) - 16:32, 13 December 2017
• sun microsystems/ultrasparc/stp1030bga-200
  |image=Ic-photo-Sun--STP1030ABGA-200--(UltraSPARC-CPU).JPG
  1 KB (179 words) - 16:32, 13 December 2017
• intel/loihi
  ...and their impact. It does this by updating the synaptic weights using the 4-bit microcode-programmed learning rules that are specifically associated with t ...or a silicon cochlea. The board communicates with a standard "super host" CPU which can be used to send commands to the board and to the management core
  12 KB (1,817 words) - 01:28, 1 October 2021
• intel/microarchitectures/cascade lake
  |atype=CPU ...(four in total) over a {{intel|UPI}} link. With two dies per package, each CPU exposes 12 DDR4 memory channels and x40 PCIe Gen3 lanes.
  32 KB (4,535 words) - 05:44, 9 October 2022
• ibm/microarchitectures/cbea
  | atype = CPU
  1 KB (121 words) - 08:18, 7 December 2017
• intel/xeon w/w-2140b
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (593 words) - 03:03, 5 January 2022
• intel/xeon w/w-2150b
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (636 words) - 11:42, 13 September 2022
• amd/cores/picasso
  ...ies of mainstream mobile and desktop APUs based on the {{amd|Zen+|l=arch}} CPU and {{amd|Vega|l=arch}} GPU microarchitectures succeeding {{\\|Raven Ridge}
  4 KB (598 words) - 14:04, 17 March 2023
• intel/microarchitectures/whiskey lake
  |atype=CPU
  5 KB (650 words) - 03:47, 9 January 2020
• intel/xeon w/w-2191b
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (673 words) - 08:21, 17 February 2021
• esperanto/microarchitectures/et-minion
  |atype=CPU
  1 KB (150 words) - 04:58, 9 February 2018
• esperanto/microarchitectures/et-maxion
  |atype=CPU
  997 bytes (119 words) - 04:58, 9 February 2018
• intel/xeon platinum/8124
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (692 words) - 08:02, 10 September 2021
• intel/xeon platinum/8124m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (747 words) - 11:20, 7 September 2021
• intel/core i7/i7-8809g
  Note that this part is fully unlocked. That is, the CPU, the GPUs, and the HBM are overclockable.
  6 KB (851 words) - 14:20, 18 June 2018
• intel/cores/kaby lake g
  ...eaving the 8 remaining lanes for other peripherals to communicate with the CPU directly.
  5 KB (728 words) - 18:07, 12 July 2018
• nvidia/tegra/xavier
  ...tandards such as Functional safety [[ISO-26262]] and [[ASIL]] level C. The CPU cluster is fully [[cache coherent]] and the coherency is extended to all th === CPU ===
  8 KB (1,263 words) - 03:08, 9 December 2019
• zhaoxin/microarchitectures/lujiazui
  |atype=CPU
  2 KB (313 words) - 12:10, 12 December 2019
• zhaoxin/microarchitectures/wudaokou
  |atype=CPU ...nstructions testing more than 300 different kinds of software, testing the CPU, GPU, memory controller, and bus.
  9 KB (1,134 words) - 13:02, 17 June 2019
• zhaoxin/microarchitectures/zhangjiang
  |atype=CPU
  1 KB (178 words) - 21:12, 15 September 2021
• via technologies/microarchitectures/isaiah
  |atype=CPU
  906 bytes (109 words) - 20:11, 15 January 2018
• via technologies/microarchitectures/isaiah ii
  |atype=CPU
  792 bytes (95 words) - 12:52, 15 January 2018
• intel/core i5/i5-8600
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (770 words) - 09:48, 24 July 2019
• samsung/microarchitectures/m1
  |atype=CPU ...]] for the sole purpose of developing high-performance, low-power, complex CPU and System IPs. A large portion of the design team consists of many ex-[[AM
  13 KB (1,962 words) - 14:48, 21 February 2019
• intel/xeon d/d-2191
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (718 words) - 23:46, 7 February 2018
• intel/xeon d/d-2166nt
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (694 words) - 00:08, 8 February 2018
• intel/xeon d/d-2161i
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (689 words) - 23:59, 7 February 2018
• intel/xeon d/d-2146nt
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (662 words) - 00:08, 8 February 2018
• intel/xeon d/d-2141i
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (657 words) - 23:53, 7 February 2018
• samsung/microarchitectures/m2
  |atype=CPU *** 16 B/cycle/CPU bandwidth
  3 KB (456 words) - 14:50, 21 February 2019
• samsung/microarchitectures/m3
  |atype=CPU
  20 KB (3,149 words) - 10:44, 15 February 2020
• intel/xeon d/d-2183it
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (727 words) - 00:08, 8 February 2018
• intel/xeon d/d-2173it
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (711 words) - 00:08, 8 February 2018
• intel/xeon d/d-2163it
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (695 words) - 00:08, 8 February 2018
• intel/xeon d/d-2143it
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (663 words) - 00:08, 8 February 2018
• intel/xeon d/d-2142it
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (663 words) - 00:08, 8 February 2018
• intel/xeon d/d-2123it
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (653 words) - 00:08, 8 February 2018
• intel/xeon d/d-2187nt
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (726 words) - 00:08, 8 February 2018
• intel/xeon d/d-2177nt
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (710 words) - 00:08, 8 February 2018
• intel/xeon d/d-2145nt
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (662 words) - 00:08, 8 February 2018
• apm/microarchitectures/skylark
  |atype=CPU
  3 KB (356 words) - 20:13, 25 September 2018
• amd/epyc embedded/3451
  ...ers and edge devices. This [[multi-chip package|multi-chip processor]] has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricat
  5 KB (771 words) - 05:20, 24 March 2023
• amd/epyc embedded/3401
  ...ers and edge devices. This [[multi-chip package|multi-chip processor]] has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricat
  5 KB (727 words) - 05:20, 24 March 2023
• amd/epyc embedded/3351
  ...ers and edge devices. This [[multi-chip package|multi-chip processor]] has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricat
  5 KB (769 words) - 05:20, 24 March 2023
• amd/epyc embedded/3301
  ...ers and edge devices. This [[multi-chip package|multi-chip processor]] has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricat
  5 KB (729 words) - 05:20, 24 March 2023
• amd/epyc embedded/3251
  ...] in early [[2018]] for dense servers and edge devices. This processor has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricat
  5 KB (752 words) - 05:15, 24 March 2023
• amd/epyc embedded/3201
  ...] in early [[2018]] for dense servers and edge devices. This processor has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricat
  5 KB (750 words) - 05:15, 24 March 2023
• amd/epyc embedded/3101
  ...] in early [[2018]] for dense servers and edge devices. This processor has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricat
  5 KB (750 words) - 05:15, 24 March 2023
• amd/epyc embedded/3151
  ...] in early [[2018]] for dense servers and edge devices. This processor has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricat
  5 KB (750 words) - 05:15, 24 March 2023
• greenwaves/gap8
  Supplementing the CPU cores is a seperate hardware convolution computation engine (HWCE) designed
  6 KB (981 words) - 14:11, 28 February 2018
• intel/microarchitectures/ice lake (server)
  |atype=CPU ...stance of::microprocessor]] [[microarchitecture::Ice Lake (server)]] [[max cpu count::1]]
  8 KB (978 words) - 18:41, 26 March 2024
• movidius/myriad/ma1110
  ** 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
  2 KB (235 words) - 15:36, 11 March 2018
• movidius/myriad/ma1100
  ** 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
  2 KB (307 words) - 13:02, 11 March 2018
• movidius/myriad/ma1101
  ** 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
  2 KB (351 words) - 22:59, 12 March 2018
• movidius/myriad/ma1102
  ** 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
  3 KB (498 words) - 22:59, 12 March 2018
• movidius/myriad/ma1133
  ** 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
  2 KB (264 words) - 15:36, 11 March 2018
• movidius/myriad/ma1135
  ** 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
  2 KB (259 words) - 15:50, 11 March 2018
• amd/zeppelin
  ...g AMD's proprietary {{amd|Infinity Fabric}}. The die consists of two {{amd|CPU Complexes}}, two DDR4 channels, USB, low-power I/O, and a series of {{amd|i
  735 bytes (113 words) - 20:06, 23 March 2018
• intel/core i5/i5-8600t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (788 words) - 09:45, 29 August 2018
• intel/microarchitectures/tremont
  |atype=CPU
  3 KB (428 words) - 19:12, 10 December 2020
• intel/microarchitectures/alder lake
  |atype=CPU ! Name !! CPU Configuration !! GPU !! Dimensions !! Area
  7 KB (975 words) - 10:38, 3 August 2023
• intel/microarchitectures/meteor lake
  |atype=CPU
  1 KB (123 words) - 15:58, 4 March 2022
• amd/cpuid
  This family covers two CPU generations. Models 00h-2Fh are first generation [[Athlon 64]] and [[Optero Having exhausted the 4-bit Base Family field, Family 0Fh introduced new CPUID semantics following the
  21 KB (3,215 words) - 13:50, 24 July 2023
• intel/cores/cascade lake sp
  ...tel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]] [[max cpu count::1]] ...tel]] [[instance of::microprocessor]] [[core name::Cascade Lake SP]] [[max cpu count::2]]
  9 KB (1,291 words) - 13:48, 27 February 2020
• intel/microarchitectures/polaris
  |atype=CPU ...AM is placed under the CPU die is to allow proper heat dissipation for the CPU die through an active cooling solution on top.
  16 KB (2,552 words) - 23:22, 17 May 2019
• amd/microarchitectures/zen 5
  |atype=CPU |core name 3=Granite Ridge (Gaming Desktop CPU)
  3 KB (324 words) - 22:33, 9 October 2022
• intel/xeon e/e-2176g
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (691 words) - 22:26, 24 April 2019
• intel/xeon e/e-2124g
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (689 words) - 22:26, 24 April 2019
• nvidia/nvlink
  ...control transmission accross multiple [[Nvidia]] [[GPU]]s and supporting [[CPU]]s. ...g over the PCIe lanes. It's worth noting that NVLink was also designed for CPU-GPU communication with higher bandwidth than PCIe. Although it's unlikely t
  9 KB (1,518 words) - 04:38, 12 April 2024
• cavium/microarchitectures/vulcan
  |atype=CPU
  17 KB (2,449 words) - 22:11, 4 October 2019
• intel/core i7/i7-8086k
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  7 KB (1,060 words) - 13:30, 11 January 2020
• intel/microarchitectures/amber lake
  |atype=CPU
  4 KB (565 words) - 09:03, 24 May 2019
• intel/cores/amber lake y
  ...solution - the [[chipset]] is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies
  4 KB (538 words) - 09:43, 27 July 2020
• samsung/microarchitectures/m4
  |atype=CPU
  5 KB (680 words) - 14:43, 16 March 2023
• intel/cores/ice lake y
  ...chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies
  5 KB (731 words) - 19:08, 26 February 2020
• intel/cores/whiskey lake u
  ...chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies
  4 KB (508 words) - 23:23, 2 August 2020
• intel/cores/ice lake u
  ...chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Communication between the separate dies
  6 KB (810 words) - 23:19, 12 May 2020
• intel/microarchitectures/comet lake
  |atype=CPU
  10 KB (1,357 words) - 18:48, 13 September 2022
• supercomputers/summit
  <tr><th>Processor</th><td>CPU</td><td>GPU</td><td>&nbsp;</td><th>Rack</th><td>Compute Racks</td><td>Stora ...ng rate to 25 GT/s, two Bricks allow for 100 GB/s of bandwidth between the CPU and GPU. In addition to everything else, there are x48 PCIe Gen 4 lanes for
  9 KB (1,496 words) - 20:39, 21 July 2019
• amd/microarchitectures/zen 4
  |atype=CPU ...erals tailored for their target market, a CCX, and a GPU. A CCX contains 8 CPU cores (fewer may be usable on some models) communicating through a shared L
  13 KB (1,821 words) - 19:28, 13 November 2023
• nvidia/microarchitectures/denver
  |atype=CPU '''Denver''' is a CPU microarchitecture from [[Nvidia]] introduced in 2014, capable of executing
  6 KB (825 words) - 09:10, 11 February 2020
• fujitsu/microarchitectures/post-k
  |atype=CPU
  675 bytes (77 words) - 11:45, 25 June 2018
• intel/microarchitectures/cooper lake
  |atype=CPU
  4 KB (477 words) - 18:40, 26 March 2024
• intel/xeon e/e-2104g
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (664 words) - 19:44, 14 May 2019
• intel/xeon e/e-2124
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  3 KB (545 words) - 10:40, 11 October 2019
• intel/xeon e/e-2126g
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (686 words) - 22:26, 24 April 2019
• intel/xeon e/e-2134
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  3 KB (545 words) - 23:08, 26 December 2019
• intel/xeon e/e-2136
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  3 KB (551 words) - 22:26, 24 April 2019
• intel/xeon e/e-2144g
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (682 words) - 22:26, 24 April 2019
• intel/xeon e/e-2146g
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (688 words) - 22:26, 24 April 2019
• intel/xeon e/e-2174g
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (684 words) - 22:26, 24 April 2019
• intel/xeon e/e-2186g
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (688 words) - 22:26, 24 April 2019
• intel/core i9/i9-9900k
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (799 words) - 23:22, 3 September 2022
• amd/cores/castle peak
  ...lly) PCIe slots and x4 M.2 NVMe/SATA SSD connectors, leveraging few of the CPU's SATA ports. One x8 PCIe link on the processor is reserved to attach the A Both the TRX40 and WRX80 offer 16 lanes (plus 8-lane CPU link) PCIe Gen 1, 2, 3, 4; 12 SATA Gen 1, 2, 3 ports, eight sharing pins wi
  7 KB (1,002 words) - 14:16, 17 March 2023
• amd/packages/socket tr4
  ..., 1.00&nbsp;mm × 0.87&nbsp;mm interstitial pitch, organic land grid array CPU package. ! || CPU Family || Microarch. || Process || Products
  86 KB (17,313 words) - 02:48, 13 March 2023
• amd/packages/socket sp3
  ..., 1.00&nbsp;mm × 0.87&nbsp;mm interstitial pitch, organic land grid array CPU package. ! || CPU Family || Microarch. || Process || Products
  110 KB (21,122 words) - 02:46, 13 March 2023
• intel/xeon gold/6138p
  ...CPU for the FPGA, providing the FPGA with a [[cache coherent]] link to the CPU. {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (881 words) - 01:14, 24 May 2019
• supercomputers/astra
  <tr><th>Processors</th><td>144<br>72 × 2 × CPU</td></tr> <tr><th>Processors</th><td>1 × CPU</td><td>2 × CPU</td></tr>
  8 KB (1,133 words) - 23:36, 2 June 2020
• arm holdings/microarchitectures/neoverse n1
  |atype=CPU
  7 KB (980 words) - 13:46, 18 February 2023
• arm holdings/microarchitectures/cortex-a76
  |atype=CPU
  14 KB (2,183 words) - 17:15, 17 October 2020
• arm holdings/microarchitectures/cortex-a77
  |atype=CPU
  17 KB (2,555 words) - 06:08, 16 June 2023
• arm holdings/microarchitectures/cortex-a78
  |atype=CPU
  21 KB (3,067 words) - 09:25, 31 March 2022
• nvidia/microarchitectures/carmel
  |atype=CPU ==== CPU Complex ====
  2 KB (280 words) - 11:27, 30 April 2019
• nanotube-ram
  ...it can be built right on top of memory or logic (e.g., NRAM on top of a [[CPU]] [[core]]) or even analog (in fact the type of device does not matter). It
  6 KB (1,010 words) - 02:42, 31 January 2019
• apm/microarchitectures/storm
  |atype=CPU * Paramesh Gopi, Gaurav Singh, Greg Favor. ''"X-Gene: 64-bit ARM CPU and SoC."'' Hot Chips 24 Symposium (HCS), 2012 IEEE. IEEE, 2012.
  2 KB (231 words) - 04:17, 26 September 2018
• intel/xeon w/w-3175x
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (770 words) - 09:39, 14 May 2021
• intel/core i9/i9-9980xe
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (771 words) - 13:52, 4 November 2019
• amd/cores/genoa
  EPYC 9004 processors identify as members of {{amd|CPUID#Family 25 (19h)|AMD CPU Family 19h, Model 11h}} (engineering samples as Model 10h). * 16 to 96 {{amd|Zen 4|l=arch}} [[x86]] CPU cores with 2-way [[SMT]]
  14 KB (1,983 words) - 01:41, 2 April 2023
• intel/xeon gold/6252
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (810 words) - 02:18, 29 December 2019
• intel/xeon gold/5220
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (743 words) - 00:22, 29 December 2019
• intel/xeon gold/6230
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (758 words) - 10:08, 19 January 2022
• intel/xeon platinum/8276m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (828 words) - 02:54, 29 December 2019
• sifive/microarchitectures/7 series
  |atype=CPU
  4 KB (625 words) - 09:16, 28 November 2018
• intel/xeon platinum/8280
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (821 words) - 02:54, 29 December 2019
• intel/xeon platinum/8280l
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (819 words) - 02:54, 29 December 2019
• intel/xeon platinum/8280m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (829 words) - 03:27, 2 March 2020
• intel/xeon platinum/8276
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (803 words) - 13:25, 8 May 2019
• intel/xeon platinum/8276l
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  6 KB (818 words) - 02:53, 29 December 2019
• intel/xeon platinum/8260
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (811 words) - 02:38, 29 December 2019
• intel/xeon platinum/8270
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (788 words) - 02:53, 29 December 2019
• intel/xeon gold/6240
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (742 words) - 03:46, 3 April 2020
• intel/xeon gold/6242
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (726 words) - 02:17, 29 December 2019
• intel/xeon gold/6240y
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (732 words) - 02:17, 29 December 2019
• nec/microarchitectures/sx-aurora
  ...each. The SPU is designed to provide all basic functionalities a typical [[CPU]]. Because the SX-Aurora is not a typical offload engine but a self-hosted ...(SPU) has to have a reasonably high performance in order to act as a host CPU for all the serial workloads including handling all the required operating
  16 KB (2,497 words) - 13:30, 15 May 2020
• intel/xeon gold/5215
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (686 words) - 12:10, 4 October 2022
• intel/xeon gold/6254
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (735 words) - 02:18, 29 December 2019
• annapurna labs/graviton/graviton
  CPU(s): 16 On-line CPU(s) list: 0-15
  7 KB (917 words) - 02:35, 12 December 2023
• cavium/microarchitectures/thunderx1
  |atype=CPU
  969 bytes (121 words) - 19:30, 1 February 2019
• cavium/thunderx/cn8890
  CPU(s): 96 On-line CPU(s) list: 0-95
  27 KB (4,202 words) - 14:32, 4 December 2018
• marvell/microarchitectures/triton
  |atype=CPU
  933 bytes (110 words) - 22:48, 20 May 2019
• intel/microarchitectures/sunny cove
  |atype=CPU Sunny Cove is Intel's microarchitecture for their [[big core|big CPU core]] which is incorporated into a number of client and server chips that
  34 KB (5,187 words) - 06:27, 17 February 2023
• intel/microarchitectures/willow cove
  |atype=CPU
  2 KB (223 words) - 09:48, 17 September 2022
• intel/microarchitectures/gracemont
  |atype=CPU
  2 KB (194 words) - 05:24, 1 September 2023
• arm holdings/microarchitectures/cortex-a15
  |atype=CPU
  3 KB (347 words) - 14:40, 31 December 2018
• arm holdings/microarchitectures/cortex-a9
  |atype=CPU
  2 KB (285 words) - 12:27, 28 July 2019
• arm holdings/microarchitectures/cortex-a8
  |atype=CPU
  3 KB (428 words) - 14:30, 31 December 2018
• arm holdings/microarchitectures/cortex-a7
  |atype=CPU ...al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circu
  2 KB (275 words) - 14:24, 31 December 2018
• arm holdings/microarchitectures/cortex-a5
  |atype=CPU
  1 KB (159 words) - 14:25, 31 December 2018
• mediatek/mt65xx/mt6595
  ...al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circu
  3 KB (358 words) - 13:44, 29 December 2018
• arm holdings/microarchitectures/arm9
  |atype=CPU
  4 KB (391 words) - 03:45, 9 October 2020
• intel/core i5/i5-9400f
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (616 words) - 16:52, 13 February 2020
• intel/core i5/i5-9600kf
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (597 words) - 09:45, 24 May 2020
• intel/core i7/i7-9700kf
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (644 words) - 14:47, 15 October 2021
• intel/core i9/i9-9900kf
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (674 words) - 05:16, 14 July 2021
• samsung/microarchitectures/m5
  |atype=CPU
  3 KB (333 words) - 22:10, 27 July 2021
• intel/microarchitectures/palm cove
  |atype=CPU
  5 KB (718 words) - 13:56, 9 May 2019
• intel/microarchitectures/golden cove
  |atype=CPU
  2 KB (261 words) - 10:14, 1 September 2022
• intel/flexible display interface
  ...ics controller present on later processors. An FDI capable southbridge and CPU pair is not usable without the existence of the appropriate video connector
  1 KB (178 words) - 00:32, 30 January 2019
• cavium/octeon tx
  <tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="4">[[Hardware Accelerators]]</t
  4 KB (483 words) - 18:35, 1 February 2019
• intel/core i9/i9-9990xe
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (601 words) - 10:27, 7 March 2022
• intel/xeon e/e-2234
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (578 words) - 17:30, 13 March 2020
• intel/xeon e/e-2236
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (583 words) - 17:32, 13 March 2020
• chip multiprocessor
  ...s a [[logic]] design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto m
  4 KB (397 words) - 15:43, 10 December 2023
• intel/xeon gold/5218
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (737 words) - 00:22, 29 December 2019
• intel/xeon gold/5222
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (660 words) - 00:53, 24 May 2019
• intel/xeon gold/6244
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (678 words) - 02:17, 29 December 2019
• intel/xeon gold/6248
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (757 words) - 02:17, 29 December 2019
• phytium/microarchitectures/mars i
  |atype=CPU
  6 KB (809 words) - 16:49, 15 October 2019
• intel/microarchitectures/rock creek
  |atype=CPU
  3 KB (340 words) - 05:23, 31 March 2019
• intel/xeon platinum/8256
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (640 words) - 02:38, 29 December 2019
• intel/xeon gold/6262v
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (763 words) - 02:18, 29 December 2019
• intel/xeon gold/6252n
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (797 words) - 02:18, 29 December 2019
• intel/xeon gold/5217
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (654 words) - 23:43, 28 December 2019
• intel/xeon gold/5218n
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (714 words) - 00:22, 29 December 2019
• intel/xeon gold/5218t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (710 words) - 00:22, 29 December 2019
• intel/xeon gold/5220s
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (723 words) - 00:22, 29 December 2019
• intel/xeon gold/5220t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (736 words) - 00:22, 29 December 2019
• intel/xeon gold/5218b
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (726 words) - 00:22, 29 December 2019
• intel/xeon gold/5215l
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (684 words) - 23:43, 28 December 2019
• intel/xeon gold/5215m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (684 words) - 23:43, 28 December 2019
• intel/core i9/i9-9880h
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (769 words) - 22:21, 11 June 2020
• intel/core i7/i7-9750h
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (718 words) - 06:36, 17 February 2023
• intel/core i9/i9-9900t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (766 words) - 12:48, 24 January 2020
• amd/cores/banded kestrel
  ...]] series of ultra-low power embedded APUs based on the {{amd|Zen|l=arch}} CPU and {{amd|Vega|l=arch}} GPU microarchitectures serving as a successor {{\\|
  3 KB (400 words) - 14:22, 17 March 2023
• intel/xeon gold/6222v
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (743 words) - 01:57, 29 December 2019
• intel/xeon gold/6226
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (703 words) - 01:57, 29 December 2019
• intel/xeon gold/6230n
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (743 words) - 01:57, 29 December 2019
• intel/xeon gold/6230t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (753 words) - 01:57, 29 December 2019
• intel/xeon gold/6234
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (673 words) - 01:58, 29 December 2019
• intel/xeon gold/6238
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (763 words) - 03:47, 25 January 2022
• intel/xeon gold/6238t
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (774 words) - 01:58, 29 December 2019
• tesla (car company)/fsd chip
  ...step]] CPU which conducts the final arbitration of the car actuators. This CPU determines if the two plans generated by the two FSD chips on the FSD compu ...until reaching a stop instruction which triggers an interrupt, letting the CPU post-process the results.
  13 KB (1,952 words) - 20:34, 16 September 2023
• hisilicon/microarchitectures/taishan v110
  |atype=CPU ...nd a '''Super IO Cluster''' ('''SICL'''). The SCCL compute dies contains 8 CPU Clusters (CCLs), memory controllers, and the L3 cache block. There are eigh
  7 KB (947 words) - 10:20, 9 September 2022
• hisilicon/hydra
  ...ay SMP, three Hydra interfaces are used per CPU with one link between each CPU, creating an all-to-all connection.
  1 KB (148 words) - 20:51, 5 May 2019
• intel/core i3/i3-9100f
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (608 words) - 00:37, 1 June 2020
• intel/xeon gold/6238l
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (758 words) - 01:58, 29 December 2019
• intel/xeon gold/6238m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (758 words) - 01:58, 29 December 2019
• intel/xeon gold/6240l
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (726 words) - 02:17, 29 December 2019
• intel/xeon gold/6240m
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (736 words) - 07:35, 10 October 2021
• intel/xeon gold/6246
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (705 words) - 02:17, 29 December 2019
• intel/xeon gold/6212u
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (793 words) - 18:45, 30 September 2021
• intel/xeon gold/6210u
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (735 words) - 14:55, 1 December 2019
• intel/xeon gold/6209u
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (726 words) - 14:56, 1 December 2019
• intel/microarchitectures/lakefield
  |atype=CPU
  5 KB (769 words) - 06:44, 14 August 2021
• intel/core i9/i9-9900ks
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  5 KB (790 words) - 23:15, 3 September 2022
• intel/xeon w/w-3275
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (621 words) - 00:26, 7 October 2019
• intel/xeon w/w-3265
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (613 words) - 15:24, 31 October 2019
• intel/xeon w/w-3223
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (646 words) - 05:36, 30 October 2019
• intel/microarchitectures/rocket lake
  |atype=CPU
  5 KB (700 words) - 12:55, 20 November 2021
• qualcomm/snapdragon 800/855 plus
  The 855+ is identical to the {{\\|855}} but features slightly higher GPU and CPU frequencies.
  6 KB (835 words) - 12:00, 17 July 2022
• arm holdings/microarchitectures/cortex-a34
  |atype=CPU
  1 KB (179 words) - 03:34, 4 December 2021
• amd/epyc/7232p
  This processor has 8 CPU cores and 32 MiB L3 cache. A single Core Complex Die (plus I/O die) can pro ...f up to DDR4-3200 memory<ref name="specs">[https://www.amd.com/en/products/cpu/amd-epyc-7232p "AMD EPYC™ 7232P"]. <i>AMD.com</i>. Retrieved October 2020
  5 KB (810 words) - 02:29, 19 August 2022
• Kirin 990
  ...t fully integrates a 5G modem ([[Balong 5000]]) in the same silicon as the CPU and the GPU. The Kirin 990 5G includes a limited version of the Balong 5000
  5 KB (660 words) - 06:32, 26 May 2022
• ibm/microarchitectures/z15
  |atype=CPU
  7 KB (912 words) - 16:31, 7 May 2020
• supercomputers/archer 2
  <tr><th>CPU</th><td>64 core AMD {{amd|Rome|l=core}} CPU @ 2.2 GHz</td></tr>
  1 KB (200 words) - 01:15, 21 October 2019
• arm holdings/microarchitectures/cortex-a710
  |atype=CPU
  728 bytes (80 words) - 13:49, 4 July 2022
• amd/cores/chagall
  ...g to OEMs. They identify as members of {{amd|CPUID#Family 25 (19h)|AMD x86 CPU Family 19h, Model 08h}}. ...pack}} and {{amd|Socket AM4|AM4|l=pack}} processors: 16 lanes (plus 8-lane CPU link) PCIe Gen 1, 2, 3, 4; 12 SATA Gen 1, 2, 3 ports, eight sharing pins wi
  8 KB (1,180 words) - 14:26, 17 March 2023
• amd/cores/dali
  ...[[AMD]] series of entry-level mobile APUs based on the {{amd|Zen|l=arch}} CPU and {{amd|Vega|l=arch}} GPU microarchitectures, a cheaper derivative of {{\
  2 KB (360 words) - 14:28, 17 March 2023
• umich/microarchitectures/vanilla-5
  |atype=CPU
  3 KB (393 words) - 18:35, 20 January 2020
• umich/microarchitectures/celerity
  |atype=CPU
  2 KB (261 words) - 01:14, 21 January 2020
• centaur/microarchitectures/cha
  |atype=CPU ...ling up to 4K-lanes of logic each cycle at the same clock frequency as the CPU cores. 4K bytes operations are available every cycle and since the NCORE is
  24 KB (3,792 words) - 04:37, 30 September 2022
• arm holdings/microarchitectures/mlp
  ...ons on the register file. The PLE features an Arm {{armh|Cortex|Cortex-M}} CPU with a 16-lane Vector Engine which supports the vector and neural network e
  9 KB (1,379 words) - 22:35, 6 February 2020
• amd/List of AMD publications
  ...8||D||[[:File:CPU Thermal Management (Am486, Am5x86, K5) (August 1995).pdf|CPU Thermal Management]]||1995-08||Am486, Am5x86, K5 ...es/TechDocs/32077c_gx_lx_pwr.pdf AMD Geode™ GX and LX Processors Typical CPU Core Power Consumption Determination]||2006-04-13||
  181 KB (24,861 words) - 16:02, 17 April 2022
• arm holdings/microarchitectures/cortex-m55
  |atype=CPU
  12 KB (1,806 words) - 10:51, 12 January 2021
• amd/packages/socket am2
  ...are compatible with Socket AM2, subject to the motherboard recognizing the CPU and the limitations of Socket AM2.
  7 KB (1,029 words) - 18:40, 22 February 2020
• amd/packages/socket am2+
  ...le with the earlier Socket AM2, subject to the motherboard recognizing the CPU, limiting its HT link to generation 1.0 mode, and using a single power plan ...re compatible with Socket AM2+, subject to the motherboard recognizing the CPU and the limitations of Socket AM2+.
  8 KB (1,212 words) - 19:01, 22 February 2020
• intel/cores/cascade lake r
  ...ntel]] [[instance of::microprocessor]] [[core name::Cascade Lake R]] [[max cpu count::2]]
  8 KB (1,098 words) - 11:25, 28 February 2020
• intel/xeon gold/6248r
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (671 words) - 08:39, 31 August 2020
• intel/xeon silver/4215r
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (648 words) - 19:00, 3 August 2022
• intel/xeon silver/4214r
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (681 words) - 11:16, 4 May 2020
• intel/xeon silver/4210r
  {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
  4 KB (663 words) - 11:21, 4 May 2020
• cea-leti/microarchitectures/tsarlet
  |atype=CPU
  12 KB (1,895 words) - 10:17, 27 March 2020
• arm holdings/microarchitectures/cortex-x1
  |atype=CPU
  7 KB (995 words) - 14:21, 4 July 2022
• amd/packages/socket am3
  ...e earlier Sockets AM2 and AM2+, subject to the motherboard recognizing the CPU and configuring its memory controller for DDR2 mode. These processors are l ...are compatible with Socket AM3, subject to the motherboard recognizing the CPU and the limitations of Socket AM3. The OPGA-940 package for Socket AM2/AM2+
  12 KB (1,960 words) - 12:23, 18 July 2020
• amd/packages/socket am3+
  ...le with the earlier Socket AM3, subject to the motherboard recognizing the CPU and the limitations of Socket AM3. The OPGA-940 package for Socket AM3/AM3+ ...re compatible with Socket AM3+, subject to the motherboard recognizing the CPU. The OPGA-940 package for Socket AM2/AM2+ differs from the OPGA-940 package
  6 KB (822 words) - 15:01, 9 December 2022
• amd/packages/ft1
  '''FT1''' was a CPU package for low power [[AMD]] microprocessors with integrated graphics targ ...are members of AMD's x86 CPU {{amd|CPUID#Family 20 (14h)|Family 14h}} with CPU cores based on the {{amd|Bobcat|l=arch}} microarchitecture, and were manufa
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• amd/packages/super socket 7
  * Pin AH32 (KEY) prevents CPU insertion into Socket 5.
  6 KB (935 words) - 09:30, 27 July 2020
• amd/packages/socket fm1
  ...ors for Socket FM1, codename "Llano", are members of AMD's Family 12h with CPU cores based on the {{amd|K10|l=arch}} microarchitecture, and were fabricate
  7 KB (1,063 words) - 15:50, 4 September 2020
• amd/packages/socket fm2
  ...2, codename "Trinity" and "Richland", are members of AMD's Family 15h with CPU cores based on the {{amd|Piledriver|l=arch}} microarchitecture, and were fa
  5 KB (727 words) - 15:34, 4 September 2020
• amd/packages/ft3
  ...name "Kabini", "Temash", and "Kyoto", are members of AMD's Family 16h with CPU cores based on the {{amd|Jaguar|l=arch}} microarchitecture, and are fabrica
  5 KB (645 words) - 16:31, 16 March 2023
• amd/packages/ft3b
  ...e", "Crowned Eagle", and "Carrizo-L", are members of AMD's Family 16h with CPU cores based on the {{amd|Puma|l=arch}} microarchitecture, and are fabricate
  4 KB (610 words) - 16:33, 16 March 2023
• amd/packages/ft4
  ...FT4 package, codename "Stoney Ridge", are members of AMD's Family 15h with CPU cores based on the {{amd|Excavator|l=arch}} microarchitecture, and are fabr
  4 KB (543 words) - 16:33, 16 March 2023
• amd/packages/socket fs1
  ...Socket FS1, codename "Llano", are members of AMD's Family 12h with 2 or 4 CPU cores based on the [[amd/microarchitectures/k10|K10]] microarchitecture, an
  4 KB (580 words) - 13:34, 7 September 2020
• amd/packages/fp3
  All processors in the FP3 package are members of AMD's Family 15h with CPU cores based on the {{amd|Steamroller|l=arch}} microarchitecture, and are fa
  5 KB (630 words) - 23:22, 25 March 2023
• amd/packages/sp1
  ...ors codenamed {{amd|Seattle|l=core}} with 8 ARM {{armh|Cortex-A57|l=arch}} CPU cores.
  3 KB (404 words) - 16:38, 16 March 2023

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