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Zen 4 - Microarchitectures - AMD
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Zen 4 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC
Process5nm, 6nm
Succession

Zen 4 is a planned microarchitecture being developed by AMD as a successor to Zen 3.

History[edit]

Zen 4 on the roadmap.

Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on November 6, 2018, AMD stated that Zen 4 was at the design completion phase.

Products[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Processor Series Cores/Threads Market
EPYC 7004 "Genoa" Up to 96/192 High-end server multiprocessors
Ryzen Threadripper 7000 "Storm Peak" Up to 96/192 Workstation & enthusiasts market processors
Ryzen 7000 "Raphael" Up to 16/32 Mainstream to high-end desktops & enthusiasts market processors
Ryzen 7000 APU "Dragon Range" Up to 16/32 High-end mobile processors with GPU
Ryzen 7000 APU "Phoenix" Up to 8/16 Mainstream desktop & mobile processors with GPU

Cores using variant Zen 4 uarch:

Processor Series Cores/Threads Market
EPYC Bergamo Up to 128/256 Cloud multiprocessors (smaller, almost half-size Zen 4c [referred to as “Zen 4D” in leaks] core sacrificing half of the L3 cache, and possibly reduced or no AVX-512)

Process Technology[edit]

Zen4 is fabricated using both the 5nm node for the Core Compute Die (CCD) and the 6nm node for the Input/Output Die (IOD) by TSMC.

Architecture[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Zen 3[edit]

  • Core
    • AVX-512 instructions support
    • L1 and L2 DTLB size increased from 64 to 72 and 2,048 to 3,072 entries
    • L2 cache doubled from 512 KiB to 1 MiB per core
    • Max. physical and linear address size raised from 48 to 52 and 57 bits respectively
    • Improved cache load, write and prefetch from/to register (less latency).
    • Higher Transistor Density, due to 5nm process
    • Capable of higher all-core clockspeeds (shown by AMD to reach 5GHz+ on all cores)
  • Package
    • Raised maximum core/thread count from 64/128 to at least 96/192 (EPYC 7004) (Bergamo supports 128 cores but preliminary data shows a slightly altered architecture featuring cores that take up less space)
    • Support for DDR5 memory and PCIe Gen 5
    • New sockets AM5 (client), SP5 (server), SP6 (server), FP7/FP7r2 (mobile)

New Instructions[edit]

Zen 4 introduced the following ISA enhancements:

Memory Hierarchy[edit]

Data and Instruction Caches[edit]

  • L0 Op Cache:
    • 4,096(?) Ops per core, 8-way(?) set associative
    • 8 Op line size(?)
    • Parity protected
  • L1I Cache:
    • 32 KiB per core, 8-way set associative
    • 64 B line size
    • Parity protected
  • L1D Cache:
    • 32 KiB per core, 8-way set associative
    • 64 B line size
    • Write-back policy
    •  ? cycles latency for Int
    •  ? cycles latency for FP
    • ECC
  • L2 Cache:
    • 1 MiB per core, 8-way set associative
    • 64 B line size
    • Write-back policy
    • Inclusive of L1(?)
    •  ? cycles latency
    • DEC-TED ECC, tag & state arrays SEC-DED
  • L3 Cache:
    • Shared by all cores in the CCX, configurable
    • 16-way set associative
    • 64 B line size
    • L2 victim cache(?)
    • Write-back policy
    •  ? cycles average load-to-use latency
    • DEC-TED ECC, tag array & shadow tags SEC-DED
    • QoS Monitoring and Enforcement

Translation Lookaside Buffers[edit]

  • ITLB
    • 64 entry L1 TLB, fully associative, all page sizes
    • 512 entry L2 TLB, ?-way set associative
      • 4-Kbyte, 2-Mbyte, and 4-Mbyte pages
    • Parity protected
  • DTLB
    • 72 entry L1 TLB, fully associative, all page sizes
    • 3,072 entry L2 TLB, 12-way set associative
      • 4-Kbyte, 2-Mbyte, and 4-Mbyte pages, PDEs to speed up table walks(?)
    • Parity protected

4-Mbyte pages require two 2-Mbyte entries in all TLBs.

System DRAM[edit]

  • EPYC 7004 "Genoa":
    • 12 channels per socket, two 40-bit DDR5 subchannels per channel
    • Up to 24 DIMMs, max. ? TiB
    • Up to PC5-41600 (DDR5-5200)
    • SR/DR RDIMM, 4R/8R LRDIMM, 3DS DIMM
    • ECC supported (x4, x8, x16, chipkill)
    • DRAM bus parity and write data CRC options

Sources: [1]

All Zen 4 Processors[edit]

 List of all Zen 4-based Processors
ModelFamilyCodenameCTL2L3BaseTurboMemoryTDPLaunchedPriceOPN
 Uniprocessors
 Multiprocessors (dual-socket)
Count: 0

Designers[edit]

  • Mike Clark(?), chief architect

Bibliography[edit]

References[edit]

  1. "Processor Programming Reference (PPR) for AMD Family 19h Models 10h, Revision A0 Processors", AMD Publ. #55901, Rev. 0.97, May 30, 2021

See Also[edit]