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EPYC 9654P - AMD
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EPYC 9654P
General Info
Model Number9654P
Part Number100-100000803,
IntroductionNovember 10, 2022 (launched)
Release Price$10625.00 (tray)
General Specs
Frequency2,400 MHz
Turbo Frequency3,550 MHz
Turbo Frequency3,700 MHz (1 core)
Clock multiplier24
ISAx86-64 (x86)
MicroarchitectureZen 4
Core NameGenoa
Core Family25
Core Model17
Core SteppingB1
Process5 nm, 6 nm
MCPYes (13 dies)
Word Size64 bit
Max Memory6 TiB
Max SMP1-Way (Uniprocessor)
TDP360 W
cTDP down320 W
cTDP up400 W
PackageSP5 (FC-OLGA)
Dimension75.4 mm × 72 mm
Pitch0.81 mm × 0.94 mm
SocketSocket SP5

EPYC 9654P is a 64-bit 96-core x86 server microprocessor designed and introduced by AMD in late 2022. This multi-chip processor, which is based on the Zen 4 microarchitecture, incorporates twelve Core Complex Dies fabricated on a TSMC 5 nm process and a large I/O die also manufactured by TSMC. The 9654P has a TDP of 360 W with a base frequency of 2.4 GHz and a boost frequency of up to 3.7 GHz. This processor supports up to 6 TiB of 12 channel DDR5-4800 memory per socket.


Main article: Zen 4 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$6 MiB
6,144 KiB
6,291,456 B
L1I$3 MiB
3,072 KiB
3,145,728 B
96 × 32 KiB8-way set associative 
L1D$3 MiB
3,072 KiB
3,145,728 B
96 × 32 KiB8-way set associativewrite-back

L2$96 MiB
98,304 KiB
100,663,296 B
0.0938 GiB
  96 × 1 MiB8-way set associativewrite-back

L3$384 MiB
393,216 KiB
402,653,184 B
0.375 GiB
  12 × 32 MiB16-way set associativewrite-back

Memory controller[edit]

Main article: Genoa § Memory Interface

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR5-4800
Supports ECCYes
Max Mem6 TiB
Max Bandwidth460.8 GB/s
264.828 GiB/s
271,183.448 MiB/s
0.259 TiB/s
0.284 TB/s
Single 38.4 GB/s
Double 76.8 GB/s
Quad 153.6 GB/s
Hexa 230.4 GB/s
Octa 307.2 GB/s
Deca 384.0 GB/s

Note one memory channel comprises two independent DDR5 subchannels with 32 data and 8 ECC lanes each.


Main article: Genoa § I/O Interfaces

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 5.0
Max Lanes: 128
SATARevision: 3.0
Max Ports: 32
USBRevision: 3.2 Gen1×1
Max Ports: 4

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
GFNISSE Galois Field New Instructions
AVXAdvanced Vector Extensions
AVX+GFNIAVX Galois Field New Instructions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_IFMAAVX-512 Integer Fused Multiply-Add
AVX512_VBMIAVX-512 Vector Bit Manipulation Instructions
AVX512_VNNIAVX-512 Vector Neural Network Instructions
AVX512_VPOPCNTDQAVX-512 Vector Population Count Doubleword and Quadword
AVX512F+GFNIAVX-512 Galois Field New Instructions
AVX512F+VAESAVX-512 Vector AES Instructions
AVX512_VBMI2AVX-512 Vector Bit Manipulation Instructions 2
AVX512_BITALGAVX-512 Bit Algorithms
AVX512F+VPCLMULQDQVector Carry-Less Multiplication of Quadwords
AVX512_BF16AVX-512 BFloat16 Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology


Facts about "EPYC 9654P - AMD"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 9654P - AMD#pcie +
base frequency2,400 MHz (2.4 GHz, 2,400,000 kHz) +
clock multiplier24 +
core count96 +
core family25 +
core model17 +
core nameGenoa +
core steppingB1 +
cpuid0x00A10F11 +
designerAMD +
die count13 +
familyEPYC +
first launchedNovember 10, 2022 +
full page nameamd/epyc/9654p +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size6,144 KiB (6,291,456 B, 6 MiB) +
l1d$ description8-way set associative +
l1d$ size3,072 KiB (3,145,728 B, 3 MiB) +
l1i$ description8-way set associative +
l1i$ size3,072 KiB (3,145,728 B, 3 MiB) +
l2$ description8-way set associative +
l2$ size96 MiB (98,304 KiB, 100,663,296 B, 0.0938 GiB) +
l3$ description16-way set associative +
l3$ size384 MiB (393,216 KiB, 402,653,184 B, 0.375 GiB) +
ldateNovember 10, 2022 +
manufacturerTSMC +
market segmentServer +
max cpu count1 +
max memory6,291,456 MiB (6,442,450,944 KiB, 6,597,069,766,656 B, 6,144 GiB, 6 TiB) +
max memory bandwidth264.828 GiB/s (460.8 GB/s, 271,183.448 MiB/s, 0.259 TiB/s, 0.284 TB/s) +
max memory channels12 +
max sata ports32 +
max usb ports4 +
microarchitectureZen 4 +
model number9654P +
nameEPYC 9654P +
packageSP5 +
part number100-100000803 + and 100-100000803WOF +
process5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) +
release price$ 10,625.00 (€ 9,562.50, £ 8,606.25, ¥ 1,097,881.25) +
release price (tray)$ 10,625.00 (€ 9,562.50, £ 8,606.25, ¥ 1,097,881.25) +
series9004 +
smp max ways1 +
socketSocket SP5 +
supported memory typeDDR5-4800 +
tdp360 W (360,000 mW, 0.483 hp, 0.36 kW) +
tdp down320 W (320,000 mW, 0.429 hp, 0.32 kW) +
tdp up400 W (400,000 mW, 0.536 hp, 0.4 kW) +
technologyCMOS +
thread count192 +
turbo frequency3,550 MHz (3.55 GHz, 3,550,000 kHz) +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +