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EPYC 9654P
General Info
Designer	AMD
Manufacturer	TSMC
Model Number	9654P
Part Number	100-100000803, 100-100000803WOF
Market	Server
Introduction	November 10, 2022 (launched)
Release Price	$10625.00 (tray)
Shop	Amazon
General Specs
Family	EPYC
Series	9004
Locked	Yes
Frequency	2,400 MHz
Turbo Frequency	3,550 MHz
Turbo Frequency	3,700 MHz (1 core)
Clock multiplier	24
CPUID	0x00A10F11
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen 4
Core Name	Genoa
Core Family	25
Core Model	17
Core Stepping	B1
Process	5 nm, 6 nm
Technology	CMOS
MCP	Yes (13 dies)
Word Size	64 bit
Cores	96
Threads	192
Max Memory	6 TiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	360 W
cTDP down	320 W
cTDP up	400 W
Packaging
Package	SP5 (FC-OLGA)
Dimension	75.4 mm × 72 mm
Pitch	0.81 mm × 0.94 mm
Contacts	6096
Socket	Socket SP5

EPYC 9654P is a 64-bit 96-core x86 server microprocessor designed and introduced by AMD in late 2022. This multi-chip processor, which is based on the Zen 4 microarchitecture, incorporates twelve Core Complex Dies fabricated on a TSMC 5 nm process and a large I/O die also manufactured by TSMC. The 9654P has a TDP of 360 W with a base frequency of 2.4 GHz and a boost frequency of up to 3.7 GHz. This processor supports up to 6 TiB of 12 channel DDR5-4800 memory per socket.

Cache

Main article: Zen 4 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 6 MiB 6,144 KiB 6,291,456 B L1I$ 3 MiB 3,072 KiB 3,145,728 B 96 × 32 KiB 8-way set associative   L1D$ 3 MiB 3,072 KiB 3,145,728 B 96 × 32 KiB 8-way set associative write-back L2$ 96 MiB 98,304 KiB 100,663,296 B 0.0938 GiB     96 × 1 MiB 8-way set associative write-back L3$ 384 MiB 393,216 KiB 402,653,184 B 0.375 GiB     12 × 32 MiB 16-way set associative write-back

Memory controller

Main article: Genoa § Memory Interface

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR5-4800 Supports ECC Yes Max Mem 6 TiB Controllers 24 Channels 12 Max Bandwidth 460.8 GB/s 429.153 GiB/s 439,453.125 MiB/s 460,800 MB/s 0.419 TiB/s 0.461 TB/s Bandwidth Single 38.4 GB/s Double 76.8 GB/s Quad 153.6 GB/s Hexa 230.4 GB/s Octa 307.2 GB/s Deca 384.0 GB/s

Note one memory channel comprises two independent DDR5 subchannels with 32 data and 8 ECC lanes each.

Expansions

Main article: Genoa § I/O Interfaces

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 5.0 Max Lanes: 128 SATA Revision: 3.0 Max Ports: 32 USB Revision: 3.2 Gen1×1 Max Ports: 4

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 SSE4a Streaming SIMD Extensions 4a GFNI SSE Galois Field New Instructions AVX Advanced Vector Extensions AVX+GFNI AVX Galois Field New Instructions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length AVX512_IFMA AVX-512 Integer Fused Multiply-Add AVX512_VBMI AVX-512 Vector Bit Manipulation Instructions AVX512_VNNI AVX-512 Vector Neural Network Instructions AVX512_VPOPCNTDQ AVX-512 Vector Population Count Doubleword and Quadword AVX512F+GFNI AVX-512 Galois Field New Instructions AVX512F+VAES AVX-512 Vector AES Instructions AVX512_VBMI2 AVX-512 Vector Bit Manipulation Instructions 2 AVX512_BITALG AVX-512 Bit Algorithms AVX512F+VPCLMULQDQ Vector Carry-Less Multiplication of Quadwords AVX512_BF16 AVX-512 BFloat16 Instructions ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG SHA SHA Extensions ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute SMT Simultaneous Multithreading AMD-Vi AMD-Vi (I/O MMU virtualization) AMD-V AMD Virtualization SME Secure Memory Encryption TSME Transparent SME SEV Secure Encrypted Virtualization SenseMI SenseMI Technology

Bibliography

• "AMD Processor Specifications". AMD.com. Retrieved February 2023.
• "AMD EPYC™ 9654P". AMD.com. Retrieved February 2023.
• "Revision Guide for AMD Family 19h Models 10h-1Fh Processors", AMD Publ. #57095, Rev. 1.00, December 9, 2022