The 7 nanometer (7 nm) lithography process is a technology node semiconductor manufacturing process following the 10 nm process node. The term "7 nm" is simply a commercial name for a generation of a certain size and its technology and does not represent any geometry of a transistor. Commercial mass production of integrated circuit using 7 nm process is set to begin sometimes in 2019 or 2020. This technology will be replaced by 5 nm process around 2022.
|Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.|
|Gate Length (Lg)|
|Contacted Gate Pitch (CPP)|
|Minimum Metal Pitch (MMP)|
|SRAM bitcell||High-Perf (HP)|
|Intel||TSMC||GlobalFoundries||Samsung||Common Platform Paper|
|P1276 (CPU), P1277 (SoC)|
|193 nm||193 nm||EUV||EUV|
|300 nm||300 nm||300 nm||300 nm||300 nm|
|Value||10 nm Δ||Value||10 nm Δ||Value||10 nm Δ||Value||10 nm Δ||Value||10 nm Δ|
On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel's 7 nm node has entered development phase and that the company's research focuses on the 5 nm and 3 nm nodes. Intel has been maintaining the details of their 7 nm node secrete for now. CEO Brian Krzanich mentioned a 2020 timeframe in an investor conference in June.
On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of EUV, the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready.
In ISSCC 2017, the memory group at TSMC detailed their test 256 MiB SRAM chip which featured a 42.64 mm² die. The chip is manufactured on TSMC's 7nm HK-MG FinFET process using 4P4E LELELELE patterning technique. The over die is 0.34x smaller than their 16 nm process version.
7 nm Microprocessors
This list is incomplete; you can help by expanding it.
7 nm Microarchitectures
- Chang, Jonathan, et al. "12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V MIN applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
- Standaert, T., et al. "BEOL process integration for the 7 nm technology node." Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2016 IEEE International. IEEE, 2016.
- Samsung/GlobalFoundries, IEEE International Electron Devices Meeting (IEDM) 2016