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5 nm lithography process

The 5 nanometer (5 nm) lithography process is a full node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2021 or 2022. The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.

Initial research[edit]

  • At the 2016 IEEE International Electron Devices Meeting (IEDM), researchers from CEA-Leti presented a paper detailing the architecture for a possible 5 nm node. The researchers presented their functional vertically stacked gate-all-around (GAA) silicon NW/NS (NanoWire/NanoSheet) MOSFETs. GAA NW transistors are a highly promising candidate to succeed FinFETs as the drive current can be optimized by vertically stacking multiple horizontal nanowires.

Industry[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


Fab
Process Name​
1st Production​
Transistor​
 ​
Fin Pitch​
Fin Width​
Fin Height​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HP)​
SRAM bit cell (HD)
Intel Common Platform TSMC
P1278?
 
FinFET
Value 7 nm Δ Value 7 nm Δ Value 7 nm Δ
 ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x ~44 nm 0.81x
 ? nm  ?x  ? nm  ?x ~32 nm 0.84x
 ? µm²  ?x  ? µm²  ?x  ? µm²  ?x
 ? µm²  ?x  ? µm²  ?x  ? µm²  ?x

5 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

5 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

References[edit]

  • TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017