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5 nm lithography process

The 5 nanometer (5 nm or 50 Å) lithography process is a technology node semiconductor manufacturing process following the 7 nm process node. Commercial integrated circuit manufacturing using 7 nm process is set to begin sometimes around 2020.

The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Industry[edit]

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Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel TSMC GlobalFoundries Samsung Common Platform Paper
P1278? (CPU), P1279? (SoC)        
         
  193 nm EUV EUV EUV
  Yes      
  LELELELE SE SE SE
Bulk Bulk Bulk Bulk Bulk
300 mm 300 mm 300 mm 300 mm 300 mm
  FinFET   FinFET GAA
         
Value 7 nm Δ Value 7 nm Δ Value 7 nm Δ Value 7 nm Δ Value 7 nm Δ
                N/A
               
               
                12 nm  
    ~44 nm 0.81x         48 nm 1.00x
    ~32 nm 0.84x            
                   
                   
                   
                   

Intel[edit]

In May of 2017, Intel's Technology and Manufacturing Group Director, Mark Bohr, confirmed that Intel was already started researching their 5 nm node as their 7nm was already in development phase.

Common Platform Alliance Paper[edit]

In a joint paper by the Common Platform (IBM, GlobalFoundries, Samsung) a 5nm node was proposed at the 2017 VLSI Symposium. The paper presents a new horizontally stacked sheet gate-all-around (GAA) FET with good properties which can be a good candidate for the replacement of FinFET at the 5nm node. The paper reports transistors with an aggressive Lg of 12 nm and a contacted poly pitch of 48 nm.

ibm stacked silicon nanowire transistors.jpg

5 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

5 nm Microarchitectures[edit]

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References[edit]

  • TSMC, Estimated at TSMC Technology Symposium, San Jose, March 15, 2017
  • Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET, 2017 Symposium on VLSI Techonlogy / Circuits