The 20 µm lithography process was the semiconductor process technology used by semiconductor companies during the mid to late 1960s. This process had an effective channel (Alu) length of roughly 20 µm between the source and drain (channel implant). The typical wafer size for this process was 0.875 inch (22 mm). The standard transistor packages those years were the TO-5 and TO-18 (Transistor Outline) metal-can packages and dual in-line packages.
|Contacted Gate Pitch|
20 µm Chips
- CD4000 Series, earliest complete family of CMOS logic circuits
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