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Ice Lake (server) - Microarchitectures - Intel
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Ice Lake (server) µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2020
Process10 nm
Instructions
ISAx86-64
Cores
Core NamesIce Lake SP,
Ice Lake X
Succession
Contemporary
Ice Lake (client)

Ice Lake (ICL) Server Configuration is Intel's successor to Cascade Lake, a 10 nm microarchitecture for enthusiasts and servers.

Codenames[edit]

Core Abbrev Target
Ice Lake X ICL-X High-end desktops & enthusiasts market
Ice Lake W ICL-W Enterprise/Business workstations
Ice Lake SP ICL-SP Server Scalable Processors

Process Technology[edit]

See also: Ice Lake (client) § Process Technology

Ice Lake will use a second-generation enhanced 10 nm process called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope.

Compiler support[edit]

Support for Ice Lake was added in LLVM Clang 6.0 and GCC 8.0.

Compiler Arch-Specific Arch-Favorable
ICC -march=icelake -mtune=icelake
GCC -march=icelake -mtune=icelake
LLVM -march=icelake -mtune=icelake
Visual Studio /? /tune:?

CPUID[edit]

Core Extended
Family
Family Extended
Model
Model
 ? 0 0x6 0x?  ?
Family 6 Model ?
 ? 0 0x6  ?  ?
Family 6 Model ?

Architecture[edit]

Key changes from Cascade Lake[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
  • Enhanced "10nm+" (from 14 nm)
  • I/O
    • PCIe 4.0 (from PCIe 3.0)
  • Memory
    • Higher bandwidth (190.7 GiB/s, up from 143.1 GiB/s)
    • Octa-channel (up from hexa-channel)
    • 3200 MT/s (up from 2933 MT/s)
  • Platform
  • Packaging
    • 4189-contact flip-chip LGA (up from 3647 contacts)

New instructions[edit]

Ice Lake introduced a number of new instructions:

  • CLWB - Force cache line write-back without flush
  • RDPID - Read Processor ID
  • Additional AVX-512 extensions:
  • TME - Total Memory Encryption
  • ENCLV - SGX oversubscription instructions
  • Fast Short REP MOV
  • Split Lock Detection

All Ice Lake Chips[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
 List of Ice Lake Processors
 Main processorFrequency/TurboMemMajor Feature Diff
ModelLaunchedPriceFamilyCore NameCoresThreadsL2$L3$TDPFrequencyMax TurboMax MemTurboSMT
 Uniprocessors
 Multiprocessors (2-way)
 Multiprocessors (4-way)
 Multiprocessors (8-way)
Count: 0
codenameIce Lake (server) +
designerIntel +
first launched2020 +
full page nameintel/microarchitectures/ice lake (server) +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameIce Lake (server) +
process10 nm (0.01 μm, 1.0e-5 mm) +