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10 nm lithography process

The 10 nanometer (10 nm) lithography process is a full node semiconductor manufacturing process following the 14 nm process stopgap. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of integrated circuit manufacturing using 10 nm process begun with risk production in late 2016 and ramped up in mid-to-late 2017. This technology is set to be replaced by 7 nm process 2019.

Industry[edit]

Announced during Intel's Technology and Manufacturing Day 2017, Intel's 10 nm process (P1274) is the first high-volume manufacturing process to employ Self-Aligned Quad Patterning (SAQP) with production starting in the second half of 2017. Intel detailed Hyper-Scaling, a marketing term for a suite of techniques used to scale a transistor, which included SAQP, a single dummy gate and contact over active gate (COAG). Samsung, which unlike Intel uses LELELE (litho-etch-litho-etch-litho-etch), plans ramp up mass production in May of 2017.

Due to marketing names the transistor sizes vary considerably between leading manufactures. For example, Intel's 10nm process is denser and smaller than TSMC's 7 nm process while Samsung's 10 nm process is more similar to Intel's 14 nm process.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel TSMC Common Platform Alliance
The Common Platform Alliance is a joint collaboration between IBM, Samsung, GlobalFoundries, STMicroelectronics, UMC
Samsung
P1274 (CPU) / P1275 (SoC)     10LPE
1st generation; 10 nm Low Power Early
, 10LPP
2nd generation; 10 nm Low Power Performance
, 10LPU
3rd generation; 10 nm Low Power Ultimate
2017 2017   2017
193 nm 193 nm 193 nm 193 nm
Yes Yes Yes Yes
SAQP   SADP LELELE
Bulk Bulk Bulk/SOI Bulk
300 mm 300 mm 300 mm 300 mm
FinFET FinFET FinFET FinFET
       
Value 14 nm Δ Value 16 nm Δ Value 14 nm Δ Value 14 nm Δ
34 nm 0.81x            
               
53 nm 1.26x            
        20 nm      
54 nm 0.77x 64 nm 0.71x 64 nm 0.80x 64 nm 0.82x
36 nm 0.69x 42 nm 0.66x 48 nm 0.75x 48 nm 0.75x
0.0441 µm² 0.62x         0.049 µm² 0.61x
0.0312 µm² 0.62x 0.042 µm² 0.57x 0.053 µm² 0.65x 0.040 µm² 0.63x
0.0367 µm² 0.62x            
               

Samsung[edit]

Samsung demonstrated their 128 Mebibit SRAM wafer from their 10nm FinFET process.

10 nm Microprocessors[edit]

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10 nm Microarchitectures[edit]

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Documents[edit]

References[edit]

  • Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.
  • Samsung uses LELELE based on their press release about their 10nm FinFET Technology on October 17, 2016.
  • Seo, K-I., et al. "A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI." VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on. IEEE, 2014.
  • Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.
  • Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).
  • Clinton, Michael, et al. "12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.