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10 nm lithography process

The 10 nanometer (10 nm) lithography process is a full node semiconductor manufacturing process following the 14 nm process stopgap. The term "10 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial mass production of integrated circuit manufacturing using 10 nm process begun in late 2016. This technology is set to be replaced by 7 nm process 2019.


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Process Name​
1st Production​
Fin Pitch​
Fin Width​
Fin Height​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HP)​
SRAM bit cell (HD)
Intel Samsung TSMC SK Hynix
P1274 10LPE
1st generation; 10 nm Low Power Early
, 10LPP
2nd generation; 10 nm Low Power Performance
, 10LPU
3rd generation; 10 nm Low Power Ultimate
2017 2017 2017 2017
Value 14 nm Δ Value 14 nm Δ Value 16 nm Δ Value 18 nm Δ
 ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
54 nm 0.77x 64 nm 0.82x 64 nm 0.71x  ? nm  ?x
 ? nm  ?x 48 nm 0.75x 42 nm 0.66x  ? nm  ?x
 ? µm²  ?x 0.049 µm² 0.61x  ? µm²  ?x  ? nm  ?x
 ? µm²  ?x 0.040 µm² 0.63x  ? µm²  ?x  ? nm  ?x


Samsung demonstrated their 128 Mebibit SRAM wafer from their 10nm FinFET process.

10 nm Microprocessors[edit]

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10 nm Microarchitectures[edit]

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  • Cho, H-J., et al. "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications." VLSI Technology, 2016 IEEE Symposium on. IEEE, 2016.
  • Song, Taejoong, et al. "A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization." IEEE Journal of Solid-State Circuits (2016).
  • Intel data Based on a presentation by Mark Bohr, Intel