From WikiChip
350 nm lithography process

The 350 nanometer lithography process (350 nm or 0.35 µm) is a full node semiconductor manufacturing process following the 500 nm process node. Commercial integrated circuit manufacturing using 350 nm process began in late 1995. 350 nm was phased out and replaced by 250 nm in 1999.

Industry[edit]

Fab
Process Name​
1st Production​
Voltage​
Metal Layers​
 ​
Gate Oxide​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Intel IBM AMD AMD DEC Fujitsu IDT NEC TI Motorola Hitachi
P854 CS-34 CS-34EX CMOS-6 CS-60 HiPerMOS 2
1994 1994 1995 1995 1996 1996 1995 1997 1996
3.3 V
4 5 5 5 4 5 3 4 5
Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ Value 500 nm Δ
6.5 nm
550 nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
880 nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
18.1 µm² 0.41x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x  ? µm²  ?x 21.67 µm²  ?x  ? µm²  ?x

Intel[edit]

DEC[edit]

DEC's 0.35 µm process, called CMOS-6, was designed at Fab-6 in Hudson, Mass. The process uses a Cobalt-Disilicide Salicide with Ldrawn of 0.35 µm with an Leff of 0.25 µm with a Tox of 6 nm. CMOS-6 was used for a number of DEC's processors such as Alpha and StrongARM. The plant was later sold to Intel where it continued to manufacture Intel's line of XScale processors.

350 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

350 nm Microcontrollers[edit]

This list is incomplete; you can help by expanding it.

350 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

References[edit]

  • Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
  • von Kaenel, Vincent, et al. "A 320 MHz, 1.5 mW@ 1.35 V CMOS PLL for microprocessor clock generation." IEEE Journal of Solid-State Circuits 31.11 (1996): 1715-1722.