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250 nm lithography process

The 250 nanometer (250 nm) lithography process is a full node semiconductor manufacturing process following the 350 nm process node. Commercial integrated circuit manufacturing using 250 nm process began in 1997 and was eventually replaced by 180 nm by 1999.

Industry[edit]

The 0.25 µm-based process entered production at Intel in 1997. Intel original 0.25 micron process was named P856 or Process 856. A second process, named P856.5, was a 5% linear shrink of the original design rules. The shrink, which enabled a high equipment re-use resulted in a smaller, 9.26 µm2, 6T SRAM. The process used 200 mm wafers, SiO2 dielectric and polysilicon electode. It used Al inter-connects and an Si channels.

Fab
Process Name​
1st Production​
Metal Layers​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
Intel IBM AMD TI DEC IDT Fujitsu TSMC Samsung Toshiba Motorola NEC
P856 CMOS-6X CS-44/CS44E/CS44E-Mod C07 CMOS-7 CMOS-10+ CS-70 HiPerMOS 4
1997 1997 1998 1999  ?  ?  ?  ? 1998 1998 1997
5 5 5 4
Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ Value 350 nm Δ
500 nm 0.91x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
640 nm 0.72x 700 nm  ?x 880 nm  ?x 850 nm  ?x 840 nm  ?x 940 nm  ?x 900 nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x  ? nm  ?x
10.26 µm2 0.57x 8.6 µm2  ?x  ? µm2  ?x 10.5 µm2  ?x 11.5 µm2  ?x 11.2 µm2  ?x  ? µm2  ?x 7.56 µm2  ?x  ? µm2  ?x  ? µm2  ?x  ? µm2  ?x 12.77 µm2  ?x

Design Rules[edit]

250 nm Microprocessors[edit]

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250 nm Microarchitectures[edit]

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