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Willow Cove - Microarchitectures - Intel
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Willow Cove µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2020
Process10 nm
Core Configs2, 4, 6, 8
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
Cores
Core NamesTiger Lake
Succession
Contemporary
Cypress Cove

Willow Cove is the successor to Sunny Cove, a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products, including Tiger Lake.

History[edit]

Intel Core roadmap

Willow Cove was originally unveiled by Intel at their 2018 architecture day. Willow Cove is intended to succeed Sunny Cove in the 2020 timeframe.

Process Technology[edit]

Willow Cove is designed to take advantage of Intel's 10 nm process (10nm SuperFin).

Architecture[edit]

Key changes from Sunny Cove

  • Expanded L2 Cache (512KB 8-way → 1.25MB 20-way)
  • 50% Expanded L3 Cache (8MB 16-way → 12MB 12-way)
  • Memory Subsystem with more bandwidth and LPDDR5 support
  • New Total Memory Encryption(TME) feature

This list is incomplete; you can help by expanding it.

New instructions[edit]

Willow Cove introduced a number of new instructions:

  • Control-flow Enforcement Technology (CET) enhancements
  • MOVDIR - Direct stores
  • Additional AVX-512 extensions:

Bibliography[edit]

  • Intel Architecture Day 2018, December 11, 2018
codenameWillow Cove +
core count2 +, 4 +, 6 + and 8 +
designerIntel +
first launched2020 +
full page nameintel/microarchitectures/willow cove +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameWillow Cove +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +