|Willow Cove µarch|
Willow Cove was originally unveiled by Intel at their 2018 architecture day. Willow Cove is intended to succeed Sunny Cove in the 2020 timeframe.
Willow Cove is designed to take advantage of Intel's 10 nm process.
Key changes from Sunny Cove
- New cache subsystem
- 3MB L3 cache per core, 50% more than Sunny Cove
- Security features
This list is incomplete; you can help by expanding it.
Willow Cove introduced a number of new instructions:
- Control-flow Enforcement Technology (CET) enhancements
MOVDIR- Direct stores
- Additional AVX-512 extensions:
AVX512_VP2INTERSECT- AVX-512 Vector Intersection Instructions
Only on server parts (Sapphire Rapids):
ENQCMD- Enqueue Stores
- Intel Architecture Day 2018, December 11, 2018
|codename||Willow Cove +|
|first launched||2020 +|
|full page name||intel/microarchitectures/willow cove +|
|instance of||microarchitecture +|
|instruction set architecture||x86-64 +|
|microarchitecture type||CPU +|
|name||Willow Cove +|
|process||10 nm (0.01 μm, 1.0e-5 mm) +|