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Sunny Cove - Microarchitectures - Intel
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Sunny Cove µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2019
Process10 nm
Core Configs2, 4
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache48 KiB/core
12-way set associative
L2 Cache512 MiB/core
8-way set associative
L3 Cache2 MiB/core
16-way set associative
Succession

Sunny Cove is the successor to Palm Cove, a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products, including Ice Lake (Client), Ice Lake (Server), Lakefield, and the Nervana NNP-I. The microarchitecture was developed by Intel's R&D Center (IDC) in Haifa, Israel.

History[edit]

Intel Core roadmap

Sunny Cove was originally unveiled by Intel at their 2018 architecture day. Intel originally intended for Sunny Cove to succeed Palm Cove in late 2017 which was it was intended to be the first 10 nm-based core and the proper successor to Skylake. Prolong delays and problems with their 10 nm process and resulted in a number of improvised derivatives of Skylake including Kaby Lake, Coffee Lake, and Comet Lake. For all practical purposes, Palm Cove has been skipped and Intel has gone directly to Sunny Cove. Sunny Cove is expected to debut in mid-2019.

14nm improv 10 delays.svg

Process Technology[edit]

Sunny Cove is designed to take advantage of Intel's 10 nm process.

Architecture[edit]

Key changes from Palm Cove/Skylake[edit]

Skylake to Sunny Cove changes
Sunny Cove enhancements
  • Front-end
    • Larger µOP cache (?, up from 1536)
  • Back-end
    • Wider allocation (5-way, up from 4-way)
    • Larger ROB (?, up from 224 entries)
    • Scheduler
      • Larger scheduler (?, up from 97 entries)
      • Larger dispatch (10-way, up from 8-way)
      • Execution ports rebalanced
      • New store data port
      • New store AGU port
  • Memory subsystem
    • LSU
      • Deeper load queue (?, up from 72 entries)
      • Deeper store queue (?, up from 42 entries)
    • Larger L1 data cache (48 KiB, up from 32 KiB)
    • Larger L2 cache (512 KiB, up from 256 KiB)
      • Larger STLBs
    • 5-Level Paging
      • Large virtual address (57 bits, up from 48i)
      • Significantly large virtual address space (128 PiB, up from 256 TiB)

This list is incomplete; you can help by expanding it.

New instructions[edit]

Sunny Cove introduced a number of new instructions:

  • CLWB - Force cache line write-back without flush
  • RDPID - Read Processor ID
  • Additional AVX-512 extensions:
  • SSE_GFNI - SSE-based Galois Field New Instructions
  • AVX_GFNI - AVX-based Galois Field New Instructions
  • Split Lock Detection - detection and cause an exception for split locks
  • Fast Short REP MOV

Overview[edit]

Sunny Cove is Intel's core microarchitecture for a series of client and server chips that succeed Palm Cove (and effectively the Skylake series of derivative). Sunny cove introduces a very large set of enhancements and improvements of its predecessor including a wider and deeper pipeline. Sunny Cove is implemented in a number of chips including Lakefield, Ice Lake (Client), and Ice Lake (Server).

Die[edit]

Core[edit]


ice lake die core.png


ice lake die core (annotated).png

Core group[edit]


ice lake die core group.png


ice lake die core group (annotated).png

Bibliography[edit]

  • Intel Architecture Day 2018, December 11, 2018