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ThunderX - Cavium
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ThunderX
Developer Cavium
Type Microprocessors
Introduction June 3, 2014 (announced)
Dec 1, 2014 (launch)
ISA ARMv8
µarch ThunderX
Word size 64 bit
8 octets
16 nibbles
Process 28 nm
0.028 μm
2.8e-5 mm
Technology CMOS
Clock 2,000 MHz-2,500 MHz
Succession
ThunderX2

ThunderX is a family of 64-bit multi-core ARM server microprocessors introduced by Cavium.

Overview[edit]

The ThunderX was Cavium's first server-class ARMv8 processor based on custom ThunderX1 core, announced in 2014. Available in single and dual socket configurations using using Cavium Coherent Processor Interconnect (CCPI™). Up to 4 DDR3/4 memory controllers.

Models[edit]

CN88xx[edit]

See also: ThunderX1 microarchitecture

The first parts of the ThunderX family, CN88xx series are based on the ThunderX1 microarchitecture. All parts have the following features in common.

  • Mem: Up to 1 TiB of quad/hexa/octa- channel DDR3/4 2400 MT/s memory
    • Up to 1 TiB in dual-socket configuration
  • ISA: ARMv8, 128-bit NEON SIMD
  • I/O: "multiple" PCIe Gen 3 Lanes
  • Only the 64-bit AArch64 execution state is support. No 32-bit AArch32 support.
 List of ThunderX1 Processors
 Main processor
ModelLaunchedCoresThreadsFrequencyPCIe Lanes
CN889031 March 201648481.9 GHz
1,900 MHz
1,900,000 kHz
24
Count: 1

See also[edit]

Facts about "ThunderX - Cavium"
designerCavium +
first announcedJune 3, 2014 +
first launchedDecember 1, 2014 +
full page namecavium/thunderx +
instance ofmicroprocessor family +
instruction set architectureARMv8 +
main designerCavium +
microarchitectureThunderX +
nameThunderX +
process28 nm (0.028 μm, 2.8e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +