ThunderX
Developer	Cavium
Type	Microprocessors
Introduction	June 3, 2014 (announced) Dec 1, 2014 (launch)
ISA	ARMv8
µarch	ThunderX
Word size	64 bit 8 octets 16 nibbles
Process	28 nm 0.028 μm 2.8e-5 mm
Technology	CMOS
Clock	2,000 MHz-2,500 MHz
Succession
	→
	ThunderX2

ThunderX is a family of 64-bit multi-core ARM server microprocessors introduced by Cavium.

Overview

The ThunderX was Cavium's first server-class ARMv8 processor based on custom ThunderX1 core, announced in 2014. Available in single and dual socket configurations using Cavium Coherent Processor Interconnect (CCPI™). Up to 4 DDR3/4 memory controllers.

Compiler Support

Compiler	Arch-Specific	Arch-Favorable	Arch-Target
GCC	-march=armv8-a	-mtune=thunderx	-mcpu=thunderx
LLVM	-march=armv8-a	-mtune=thunderx	-mcpu=thunderx

Models

CN88xx

See also: ThunderX1 microarchitecture

The first parts of the ThunderX family, CN88xx series are based on the ThunderX1 microarchitecture. All parts have the following features in common.

• Mem: Up to 1 TiB of quad/hexa/octa- channel DDR3/4 2400 MT/s memory
  • Up to 1 TiB in dual-socket configuration
• ISA: ARMv8, 128-bit NEON SIMD
• I/O: "multiple" PCIe Gen 3 Lanes
• Only the 64-bit AArch64 execution state is support. No 32-bit AArch32 support.

	List of ThunderX1 Processors
	Main processor
Model	Launched	Cores	Threads	Frequency	PCIe Lanes
CN8890	31 March 2016	48	48	1.9 GHz 1,900 MHz 1,900,000 kHz
Count: 1

See also

• ThunderX® ARM Processors Archive
• Investigating Cavium's ThunderX: The First ARM Server SoC With Ambition
• Exploring a production Cavium ThunderX platform with a Gigabyte R120-T30 1U server
• TIRIAS ThunderX Memecached TCO white paper
• Qualcomm's Centriq
• Intel's Xeon Platinum, Gold, and Silver
• Cavium ThunderX2.