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Zen 3 - Microarchitectures - AMD
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Zen 3 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC, GlobalFoundries
IntroductionOctober 8, 2020
Process7nm, 12 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages19
Decode4-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SHA, UMIP, CLZERO
Succession

Zen 3 is a microarchitecture being developed by AMD as a successor to Zen 2.

History[edit]

amd zen future roadmap.jpg

Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the Zen microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize 7nm+ process.

Codenames[edit]

amd zen2-3 roadmap.png
Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core C/T Target
Milan 64/128 High-end server multiprocessors
Genesis Peak  ?/? Workstation & enthusiasts market processors
Vermeer 16/32 Mainstream to high-end desktops & enthusiasts market processors
Cezanne  ?/? Mainstream desktop & mobile processors with GPU

Process technology[edit]

Zen 3 will be fabricated on TSMC's 7nm+ process.

Architecture[edit]

There is very limited information available about the architectural improvements of Zen 3.

Key changes from Zen 2[edit]

  • +19% IPC
  • Unified 8-core CCX with 32 MiB L3$ available to all 8 cores equally. Latency increased by roughly 7 cycles (18%) to an average of 46 cycles.
  • Integer unit:
    • Integer physical register file increased from 180 to 192 entries
    • Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways.
    • Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each.
    • Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams.
    • 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately.
  • Floating point unit:
    • FMA latency reduced by 1 cycle from 5 to 4.
    • Fourth and fifth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.
    • Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set.
    • 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughout.
    • Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.
  • Load/store:
    • Load throughput increased from 2 to 3, if not 256b.
    • Store throughput increased from 1 to 2, if not 256b.
    • Store queue increase from 48 to 64 slots.
    • Page table walkers tripled from 2 to 6 for TLB miss handling.
  • Improved prefetching
  • Increased branch prediction bandwidth
    • "zero-bubble" branch prediction
    • L1 BTB doubled from 512 to 1024 entries
  • Improved µop cache

This list is incomplete; you can help by expanding it.

All Zen 3 Chips[edit]

 List of all Zen 3-based Processors
 ProcessorFeatures
ModelPriceProcessLaunchedFamilyCoreCTTDPL3BaseTurboMax MemSMTSEVSMETSME
 Uniprocessors
Ryzen 5 5600X$ 299.00
€ 269.10
£ 242.19
¥ 30,895.67
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
5 November 2020Ryzen 5Vermeer61265 W
65,000 mW
0.0872 hp
0.065 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.7 GHz
3,700 MHz
3,700,000 kHz
4.6 GHz
4,600 MHz
4,600,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
Ryzen 7 5800X$ 449.00
€ 404.10
£ 363.69
¥ 46,395.17
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
5 November 2020Ryzen 7Vermeer816105 W
105,000 mW
0.141 hp
0.105 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
4.7 GHz
4,700 MHz
4,700,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
Ryzen 9 5900X$ 549.00
€ 494.10
£ 444.69
¥ 56,728.17
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
5 November 2020Ryzen 9Vermeer1224105 W
105,000 mW
0.141 hp
0.105 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.7 GHz
3,700 MHz
3,700,000 kHz
4.8 GHz
4,800 MHz
4,800,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
Ryzen 9 5950X$ 799.00
€ 719.10
£ 647.19
¥ 82,560.67
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
5 November 2020Ryzen 9Vermeer1632105 W
105,000 mW
0.141 hp
0.105 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.4 GHz
3,400 MHz
3,400,000 kHz
4.9 GHz
4,900 MHz
4,900,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
 Multiprocessors (dual-socket)
Count: 4

Designers[edit]

  • Mark Evers, Chief Architect

Bibliography[edit]

  • AMD 'Tech Day', February 22, 2017
  • AMD 2017 Financial Analyst Day, May 16, 2017

See Also[edit]

codenameZen 3 +
designerAMD +
first launchedOctober 8, 2020 +
full page nameamd/microarchitectures/zen 3 +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerTSMC + and GlobalFoundries +
microarchitecture typeCPU +
nameZen 3 +
pipeline stages19 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +