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Rome
General Info
Designer	AMD
Manufacturer	TSMC, GlobalFoundries
Introduction	May 16, 2017 (announced)
Microarchitecture
ISA	x86-64
Microarchitecture	Zen 2
Word Size	8 octets 16 nibbles 64 bit
Process	14 nm 0.014 μm 1.4e-5 mm , 7 nm 0.007 μm 7.0e-6 mm
Technology	CMOS
Packaging
Package	FCLGA-4094 (LGA)
Dimension	58.5 mm × 75.4 mm
Pitch	1.00 mm
Contacts	4094
Socket	Socket SP3, LGA-4094
Succession
Naples Milan

Rome codename for AMD's high-performance enterprise-level server multiprocessors based on the Zen 2 microarchitecture serving as a successor to Naples. Rome-based chips are fabricated on TSMC 7 nm process with some components made on GlobalFoundries 14 nm process.

AMD datacenter roadmap

Overview

AMD Rome system on chips are a series of high-performance multiprocessors designed by AMD based on their Zen 2 microarchitecture. Rome SoCs support both single and 2-way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs support 128 PCIe lanes each, however, half of them are lost when in 2-way MP (leaving the system with the same overall lanes count as a single socket solution). Communication between the two chips is done via AMD's Infinity Fabric protocol over the 64 reserved lanes. Rome is backwards platform/socket compatible with Naples and forward-compatible with Milan.

Common Features

All Rome processors have the following:

• 128 PCIe lanes (in both single-way and dual-way multiprocessing)
  • PCIe Gen 4
• Octa-channel Memory
  • Up to DDR4-2933 ECC
  • Up to 4 TiB (8 TiB in 2MP)
• Up to 64 cores / 128 threads
• Everything up to AVX2 (i.e., SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2), and SHA

Rome Processors

	List of Rome Processors
Model	Family	Price	Launched	Cores	Threads	TDP	L2$	L3$	Base	Turbo
Count: 0

See also

Zen 2 Rome Matisse Renoir

Power/Performance