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Rome - Cores - AMD
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General Info
ManufacturerTSMC, GlobalFoundries
IntroductionMay 16, 2017 (announced)
MicroarchitectureZen 2
Word Size
8 octets
16 nibbles
64 bit
Process14 nm
0.014 μm
1.4e-5 mm
, 7 nm
0.007 μm
7.0e-6 mm
PackageFCLGA-4094 (LGA)
Dimension58.5 mm × 75.4 mm
Pitch1.00 mm
SocketSocket SP3, LGA-4094

Rome codename for AMD's high-performance enterprise-level server multiprocessors based on the Zen 2 microarchitecture serving as a successor to Naples. Rome-based chips are fabricated on TSMC 7 nm process with some components made on GlobalFoundries 14 nm process.

AMD datacenter roadmap


AMD Rome system on chips are a series of high-performance multiprocessors designed by AMD based on their Zen 2 microarchitecture. Rome SoCs support both single and 2-way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs support 128 PCIe lanes each, however, half of them are lost when in 2-way MP (leaving the system with the same overall lanes count as a single socket solution). Communication between the two chips is done via AMD's Infinity Fabric protocol over the 64 reserved lanes. Rome is backwards platform/socket compatible with Naples and forward-compatible with Milan.

Common Features[edit]

All Rome processors have the following:

Rome Processors[edit]

 List of Rome Processors
Count: 0

See also[edit]

arrow up 1.svgPower/Performance

Facts about "Rome - Cores - AMD"
designerAMD +
first announcedMay 16, 2017 +
instance ofcore +
isax86-64 +
manufacturerTSMC + and GlobalFoundries +
microarchitectureZen 2 +
nameRome +
packageFCLGA-4094 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket SP3 + and LGA-4094 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +