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EPYC 7H12 - AMD
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EPYC 7H12
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
Model Number7H12
MarketServer
IntroductionSeptember 18, 2019 (announced)
September 18, 2019 (launched)
General Specs
FamilyEPYC
Series7002
LockedYes
Frequency2,600 MHz
Turbo Frequency3,300 MHz
Clock multiplier26
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen 2
Core NameRome
Core Family23
Process7 nm, 14 nm
TechnologyCMOS
MCPYes (9 dies)
Word Size64 bit
Cores64
Threads128
Max CPUs2 (Multiprocessor)
Max Memory4 TiB
Electrical
TDP280 W
Packaging
PackageFCLGA-4094 (LGA)
Dimension58.5 mm × 75.4 mm
Pitch1.00 mm
Contacts4094
SocketSocket SP3, LGA-4094

EPYC 7H12 is a 64-bit 64-core x86 server microprocessor designed and introduced by AMD in late 2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7H12 has a TDP of 280 W with a base frequency of 2.6 GHz and a boost frequency of up to 3.3 GHz. This processor supports up to two-way SMP and up to 4 TiB of eight channels DDR4-3200 memory per socket.

This is a specially-binned microprocessor intended for the HPC market. Due to the high TDP requirement, this SKU is intended to be liquid-cooled.

Cache[edit]

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
L1I$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
64x32 KiB8-way set associative 
L1D$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
64x32 KiB8-way set associative 

L2$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  64x512 KiB8-way set associativewrite-back

L3$256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
  16x16 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

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Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCYes
Max Mem4 TiB
Controllers8
Channels8
Max Bandwidth190.7 GiB/s
Bandwidth
Single 23.84 GiB/s
Double 47.68 GiB/s
Quad 95.37 GiB/s
Hexa 143.1 GiB/s
Octa 190.7 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

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Expansion Options
PCIeRevision: 4.0
Max Lanes: 128
Configuration: x16, x8


Features[edit]

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology
Boost 2Precision Boost 2
Facts about "EPYC 7H12 - AMD"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7H12 - AMD#pcie +
base frequency2,600 MHz (2.6 GHz, 2,600,000 kHz) +
clock multiplier26 +
core count64 +
core family23 +
core nameRome +
designerAMD +
die count9 +
familyEPYC +
first announcedSeptember 18, 2019 +
first launchedSeptember 18, 2019 +
full page nameamd/epyc/7h12 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd precision boost 2true +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l1d$ description8-way set associative +
l1d$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l1i$ description8-way set associative +
l1i$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l2$ description8-way set associative +
l2$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
l3$ size256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) +
ldateSeptember 18, 2019 +
manufacturerTSMC + and GlobalFoundries +
market segmentServer +
max cpu count2 +
max memory4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory channels8 +
microarchitectureZen 2 +
model number7H12 +
nameEPYC 7H12 +
packageFCLGA-4094 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
series7002 +
socketSocket SP3 + and LGA-4094 +
supported memory typeDDR4-3200 +
tdp280 W (280,000 mW, 0.375 hp, 0.28 kW) +
technologyCMOS +
thread count128 +
turbo frequency3,300 MHz (3.3 GHz, 3,300,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +