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Exynos M2 - Microarchitectures - Samsung
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Mongoose 2 µarch
General Info
Arch TypeCPU
DesignerSamsung
ManufacturerSamsung
IntroductionFebruary 23, 2017
Phase-out2018
Process10 nm
Core Configs4
Pipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14
Decode4-way
Instructions
ISAARMv8
Cache
L1I Cache64 KiB/core
4-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache2 MiB/cluster
16-way set associative
Succession

Exynos Mongoose 2 (M2) is the successor to the Mongoose 1, a 10 nm ARM microarchitecture designed by Samsung for their consumer electronics.

Process Technology

M2 was fabricated on Samsung's first generation 10LPE (Low Power Early) process.

Compiler support

Compiler Arch-Specific Arch-Favorable
GCC -mcpu=exynos-m1 -mtune=exynos-m1
LLVM -mcpu=exynos-m2 -mtune=exynos-m2

Architecture

Key changes from Mongoose 1

This list is incomplete; you can help by expanding it.

Block Diagram

Core Cluster Overview

(Cluster identical to Mongoose 1)

mongoose 1 soc block diagram.svg

Individual Core

mongoose 2 block diagram.svg

Memory Hierarchy

  • Cache
    • L1I Cache
      • 64 KiB, 4-way set associative
        • 128 B line size
        • per core
      • Parity-protected
    • L1D Cache
      • 32 KiB, 8-way set associative
        • 64 B line size
        • per core
      • 4 cycles for fastest load-to-use
      • 16 B/cycle load bandwidth
      • 16 B/cycle store bandwidth
    • L2 Cache
      • 2 MiB, 16-way set associative
        • 4x banks (512 KiB each)
      • Inclusive of L1
      • 22 cycles latency
      • 16 B/cycle/CPU bandwidth

The M2 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).

  • TLBs
    • ITLB
      • 256-entry
    • DTLB
      • 32-entry
    • STLB
      • 1,024-entry
      • Per core
  • BPU
    • 4K-entry main BTB
    • 64-entry µBTB
    • 64-entry return stack
    • 8K-entry L2 BTB

Core

The M2 core is almost identical to the M1.

All M2 Processors

 List of M2-based Processors
 Main processorIntegrated Graphics
ModelFamilyLaunchedArchCoresFrequencyTurboGPUFrequency
8895Exynos29 March 2017Mongoose 2, Cortex-A5381.7 GHz
1,700 MHz
1,700,000 kHz
, 2.314 GHz
2,314 MHz
2,314,000 kHz
Count: 1
codenameMongoose 2 +
core count4 +
designerSamsung +
first launchedFebruary 23, 2017 +
full page namesamsung/microarchitectures/m2 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerSamsung +
microarchitecture typeCPU +
nameMongoose 2 +
phase-out2018 +
pipeline stages14 +
process10 nm (0.01 μm, 1.0e-5 mm) +