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Tremont - Microarchitectures - Intel
Edit Values Tremont µarch Arch Type CPU Designer Intel Manufacturer Intel Introduction 2018/2019 Process 14/10 nm Type Superscalar OoOE Yes Speculative Yes Reg Renaming Yes ISA x86-64 Extensions MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA Core Names Gemini Lake
Tremont is Intel's successor to Goldmont Plus, a 14 nm or 10 nm microarchitecture for ultra-low power devices and microservers.
Codenames [ edit ]
Release Dates [ edit ]
Technology [ edit ]
Tremont appear to be planned for Intel's
10 nm process.
Compiler support [ edit ]
Family 6 Model 134
Architecture [ edit ]
Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
New instructions [ edit ]
Tremont introduced a number of
- Force cache line write-back without flush
- SGX oversubscription instructions
- Cache line demote instruction
- SSE-based Galois Field New Instructions
Direct store instructions: MOVDIRI, MOVDIR64B
User wait instructions: TPAUSE, UMONITOR, UMWAIT
Split Lock Detection - detection and cause an exception for split locks