From WikiChip
Tremont - Microarchitectures - Intel
< intel‎ | microarchitectures

Edit Values
Tremont µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2018/2019
Process14/10 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, SHA
Cores
Core NamesGemini Lake
Succession

Tremont is Intel's successor to Goldmont Plus, a 14 nm or 10 nm microarchitecture for ultra-low power devices and microservers.

Codenames[edit]

Platform Core Name
Jacobsville Elkhart Lake?

Brands[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Release Dates[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Technology[edit]

Tremont appear to be planned for Intel's 10 nm process.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
ICC -march=tremont -mtune=tremont
GCC -march=tremont -mtune=tremont
LLVM -march=tremont -mtune=tremont
Visual Studio /arch:? /tune:?

CPUID[edit]

Core Extended
Family
Family Extended
Model
Model
 ? 0 0x6 0x8 0x6
Family 6 Model 134

Architecture[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from Goldmont Plus[edit]

New instructions[edit]

Tremont introduced a number of new instructions:

  • CLWB - Force cache line write-back without flush
  • ENCLV - SGX oversubscription instructions
  • CLDEMOTE - Cache line demote instruction
  • SSE_GFNI - SSE-based Galois Field New Instructions
  • Direct store instructions: MOVDIRI, MOVDIR64B
  • User wait instructions: TPAUSE, UMONITOR, UMWAIT
  • Split Lock Detection - detection and cause an exception for split locks