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3 nm lithography process
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The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing process following the 5 nm process node. Commercial integrated circuit manufacturing using 3 nm process is set to begin sometimes around 2023.

The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and does not represent any geometry of the transistor.

Industry[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel TSMC Samsung
P1280? (CPU), P1281? (SoC)   3GAAE
3nm Gate All Around Early
     
EUV EUV EUV
     
SE SE SE
Bulk Bulk Bulk
300 mm 300 mm 300 mm
    GAA
     
Value 5 nm Δ Value 5 nm Δ Value 5 nm Δ
        N/A
       
       
           
           
           
           
           
           
           

Samsung[edit]

On May 24 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET (MBCFET), an extension of a Gate-all-around (GAA) FET. This is planned for somewhere after the 5nm node but the exact timeline or specification is currently unknown.

3 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

3 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.

References[edit]

  • Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017