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22 nm lithography process

The 22 nanometer (22 nm) lithography process is a full node semiconductor manufacturing process following the 28 nm process stopgap. The term "22 nm" is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch. Commercial integrated circuit manufacturing using 22 nm process began in 2008 for memory and 2012 for MPUs. This technology was replaced by with 20 nm process (HN) in 2014 and 16 nm process (FN) in late 2015.

Industry[edit]

The 22 nm became Intel's first generation of Tri-gate FinFET transistors and the first such transistor on the market. This process became 3rd generation high-k + metal gate transistors for Intel. In 2017 Intel announce the introduction of a new process "22FFL" specifically for low power IOT and mobile products for their custom foundry.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel Intel IBM
P1270 (CPU) / P1271 (SoC) 22FFL 22HP
2011 2017 2013
193 nm 193 nm 193
Yes Yes Yes
SADP SADP  
Bulk Bulk SOI
300 mm 300 mm 300 mm
FinFET FinFET Planar
0.75 V    
Value 32 nm Δ Value 32 nm Δ Value 32 nm Δ
60 nm N/A 45 nm N/A N/A
8 nm  
34 nm  
26 nm 30 nm 25-33 nm 0.83-1.1x
90 nm 0.80x 108 nm 100 nm 0.79x
80 nm 0.71x 90 nm 80 nm 0.80x
0.130 µm² 0.65x   0.144 µm²  
0.092 µm² 0.62x 0.088 µm² 0.128 µm² 0.86x
0.108 µm² 0.63x      
0.029 µm²     0.026 µm² 0.67x

Intel[edit]

intel 22nm tri-gate transistors.png


Find models[edit]

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22 nm Microprocessors[edit]

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22 nm Microarchitectures[edit]

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Documents[edit]

References[edit]

  • Narasimha, S., et al. "22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL." Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012.
  • Natarajan, S., et al. "A 14nm logic technology featuring 2 nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
  • Hamzaoglu, Fatih, et al. "13.1 a 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. IEEE, 2014.