|Core Configs||1, 2, 4, 8|
|Extensions||MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND|
|L1I Cache||32 KiB/Core|
8-way set associative
|L1D Cache||24 KiB/Core|
6-way set associative
|L2 Cache||1 MiB/2 Cores|
16-way set associative
Silvermont (SLM) is Intel's 22 nm microarchitecture for the Atom family of system on chips. Introduced in 2013, Silvermont was the successor to Saltwell, targeting smartphones, tablets, embedded devices, and consumer electronics.
- 1 Codenames
- 2 Process Technology
- 3 Architecture
- 4 Die
- 5 Cores
- 6 All Silvermont Chips
|Slayton||SoFIA||Smartphones (3G only)|
|Bay Trail||Bay Trail||Tablets|
- Main article: Ivy Bridge § Process Technology
Silvermont-based chips are manufactured on Intel's 22 nm process.
- Pipeline is now OoOE
- 14 stage (2 shorter)
- 10 stage panelty for miss (3 shorter)
- Support up to Westmere
- Multi-core modular system (up to 8 cores)
Silvermont introduced a number of new instructions:
SSE4.1- Streaming SIMD Extensions, Version 4.1
SSE4.2- Streaming SIMD Extensions, Version 4.2
MOVBE- Move Big-Endian instruction
CRC32- Hardware-accelerated CRC32
POPCNT- Hardware-accelerated population count
CLMUL- Hardware-accelerated Carry-less Multiplication
AES- Hardware-accelerated AES operations
RDRAND- Secure Key Technology extension
PREFETCHW- Prefetch data into caches, hinting a write is expected in the future
Silvermont employs a modular core design. Each module consists of 2 cores and 2 threads with exclusive hardware - resources are not shared. Within each module is a 1 MB L2 cache shared between the two cores. The L1 is still identical to Saltwell's: 32K L1I$ and 24K L1D$. Each module as a dedicated point-to-point interface (IDI) to the system agent. Each module has a per-core frequency and power management support. This is a departure from previous microarchitectures as well as similar desktop (e.g. Core) where all cores are tied to the same frequency.
The system agent (Silvermont System Agent') acts very much like a North Bridge however it does a much better job than previous Atom microarchitectures performance-wise because it's capable of reordering all requests from all consumers (e.g. Core, GPU).
While the previous Atom architecture did away with the memory controller by integrating and other support chips on-die, it still used a Front Side Bus implementation to talk to North Bridge. In Silvermont, this was replaced with a lightweight in-die interconnect (IDI) - same one used in the Core processors. The use of IDI should have noticeable performance impact per thread.
- Hardware prefetchers
- L1 Cache:
- L2 Cache:
- 1 MiB 16-way set associative, 64 B line size
- Per 2 cores
- 32B/cycle, 14 cycle latency
- L3 Cache:
- No level 3 cache
- Maximum of 1 GiB, 2 GiB, and 4 GiB
- dual 32-bit channels, 1 or 2 ranks per channel
Silvermont dropped support for Intel Hyper-Threading Technology.
While Silvermont share some similarities with Saltwell, it introduces a number of significant changes that sets it apart from part Atom microarchitectures. Like Saltwell, the pipeline is still uses a dual-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchitecture to introduce out-of-order execution (OoOE)
Silvermont pipeline decodes and issues 2 instructions and dispatches 5 operations/cycle.
Instruction Fetch, just like in previous microarchs make up the first three stages of the pipeline. However, with the introduction of out-of-order execution, silvermont's more aggressive fetching and branch prediction mean stalled instructions do not clog the entire pipeline as it did in Saltwell.
In previous generations of microarchitectures, common software code had roughly 5% of instructions split up into micro-ops. In Silvermont this is reduced down to just 1-2%. This reduction translates directly into performance because it eliminates the 3-4 additional cycles of overhead. Silvermont has a second branch predictor that can make more accurate predictions based on previously unknown information (e.g. target address from memory or register) and override the generic predictor. Nevertheless the expense of branch misprediction penalties was also reduced by 3 stages (down to 10 cycles from 13 in Saltwell).
Silvermont has two branch predictions: one that controls the instruction fetching and a second one that can override the first during the decode stage after gather additional information. The second predictor controls the speculative instruction issuing. For the first predictor, Silvermont uses a Branch Target Buffer to determine the next fetch address which also includes a 4-entry Return Stack Buffer for calls and returns handling.
8-core Avoton Die:
- Tangier - SoCs for Smartphones
- Valleyview - SoCs for Tablets
- Avoton - SoCs for Microservers
- Rangeley - SoCs for Embedded Networking
All Silvermont Chips
|Model||µarch||Platform||Core||Launched||SDP||TDP||Freq||Max Mem||Name||Freq||Max Freq|
|x3-C3130||Silvermont||SoFIA||SoFIA||4 March 2015||1,000 MHz|
|Mali-400 MP2||480 MHz|
|x3-C3200RK||Silvermont||SoFIA||SoFIA||4 March 2015||2 W|
|Mali-450 MP4||600 MHz|
|x3-C3230RK||Silvermont||SoFIA||SoFIA||4 March 2015||2 W|
|Mali-450 MP4||600 MHz|
|x3-C3405||Silvermont||SoFIA||SoFIA||April 2015||2 W|
|Mali T720 MP2||456 MHz|
|x3-C3445||Silvermont||SoFIA||SoFIA||April 2015||2 W|
|Mali T720 MP2||456 MHz|
|core count||1 +, 2 +, 4 + and 8 +|
|first launched||2013 +|
|full page name||intel/microarchitectures/silvermont +|
|instance of||microarchitecture +|
|instruction set architecture||x86-64 +|
|microarchitecture type||CPU +|
|pipeline stages (max)||14 +|
|pipeline stages (min)||12 +|
|process||22 nm (0.022 μm, 2.2e-5 mm) +|