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32 nm lithography process

The 32 nanometer (32 nm) lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry[edit]

TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the self-aligned via patterning.


 
Process Name
1st Production
Lithography Lithography
Immersion
Exposure
Wafer Type
Size
Transistor Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
Intel TSMC Common Platform Alliance
The Common Platform Alliance 20 nm node was a collaboration between IBM, Samsung, Freescale, Toshiba, Chartered Semiconductor Manufacturing, Infineon Technologies
Toshiba / NEC Common Platform Alliance (SOI)
P1268 (CPU) / P1269 (SoC)        
2009   2011    
193 nm 193 nm 193 nm 193 nm 193 nm
Yes Yes Yes Yes Yes
DP DP DP DP DP
Bulk Bulk Bulk Bulk SOI
300 mm 300 nm 300 nm 300 nm 300 nm
Planar Planar Planar Planar Planar
1 V, 0.75 V 1.1 V 1 V, 0.8 V 1 V 1 V
9   11   11
Value 45 nm Δ Value 40 nm Δ Value 45 nm Δ Value 40 nm Δ Value 45 nm Δ
30 nm   30 nm   30 nm       25 nm  
112.5 nm 0.63x 130 nm   126 nm   120 nm   130 nm  
112.5 nm 0.70x 100 nm   100 nm   100 nm   100 nm  
0.199 µm²                  
0.148 µm²   0.15 µm²   0.157 µm²   0.124 µm²   0.149 µm²  
0.171 µm²                  
                0.039 µm²  

Design Rules[edit]

Find models[edit]

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32 nm Microprocessors[edit]

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32 nm Microarchitectures[edit]

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Documents[edit]

References[edit]

  • Greene, B., et al. "High performance 32nm SOI CMOS with high-k/metal gate and 0.149 µm 2 SRAM and ultra low-k back end with eleven levels of copper." VLSI Technology, 2009 Symposium on. IEEE, 2009.
  • Jan, C-H., et al. "A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
  • Wu, Shien-Yang, et al. "A 32nm CMOS low power SoC platform technology for foundry applications with functional high density SRAM." Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE, 2007.
  • Chen, X., et al. "A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process." VLSI Technology, 2008 Symposium on. IEEE, 2008.
  • Diaz, C. H., et al. "32nm gate-first high-k/metal-gate technology for high performance low power applications." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
  • Natarajan, S., et al. "A 32nm logic technology featuring 2 nd-generation high-k+ metal-gate transistors, enhanced channel strain and 0.171 μm 2 SRAM cell size in a 291Mb array." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
  • Hasegawa, S., et al. "A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
  • Arnaud, F., et al. "32nm general purpose bulk CMOS technology for high performance applications at low voltage." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.
  • Pilo, Harold, et al. "A 64 Mb SRAM in 32 nm high-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements." IEEE Journal of Solid-State Circuits 47.1 (2012): 97-106.