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32 nm lithography process

The 32 nanometer (32 nm) lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry[edit]

TSMC cancelled its planned 32nm node process.

Fab
Process Name​
1st Production​
Type​
Wafer​
 ​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell (HD)​
SRAM bit cell (HS)​
SRAM bit cell (LP)​
DRAM bit cell
Common Platform Intel TSMC Samsung Toshiba / NEC Common Platform 2
P1268 (CPU) / P1269 (SoC) 32LP
2009 2009 2009 2009 2009 2010
PDSOI Bulk
300mm
Value 45 nm Δ Value 45 nm Δ Value 40 nm Δ Value 40 nm Δ Value 40 nm Δ Value 45 nm Δ
130 nm 0.68x 112.5 nm 0.63x 130 nm 0.80x 126 nm 0.98x 120 nm 0.71x 126 nm 0.66x
 ? nm  ?x 112.5 nm 0.70x 100 nm 0.83x 100 nm 0.85x  ? nm  ?x 100 nm  ?x
0.15 µm2 0.41x 0.148 µm2 0.43x 0.15 µm2 0.62x 0.149 µm2  ?x 0.124 µm2 0.64x 0.157 µm2 0.42x
0.199 µm2
0.171 µm2 0.45x
0.039 µm2 0.58x

Design Rules[edit]

Find models[edit]

Click to browse all 32 nm MPU models

32 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

32 nm Microarchitectures[edit]

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References[edit]

  • Samsung foundry solution for 32 & 28 nm
  • Diaz, C. H., et al. "32nm gate-first high-k/metal-gate technology for high performance low power applications." Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE, 2008.