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5 µm lithography process

The 5μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process was later superseded by 3 µm, 2 µm, and 1.5 µm processes.


HP's NMOS II process as the name implied was a second generation nMOD process which was a shrink of their previous generation 7 µm nMOS also developed by HP's Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the NMOS III using a 1.5 µm process. While they succeeded in doubling the density and more than ten-folding the speed, the complexity of the chip still required them to fabricate it on 3 seperate dies and package them together.

Process Name​
1st Production​
Contacted Gate Pitch​
Interconnect Pitch​
Metal Layers​
 ? nm
 ? nm
51 mm

5µm Microprocessors[edit]

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