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5 µm lithography process

The 5μm lithography process was the semiconductor process technology used by some semiconductor companies during the mid 1970s. This process was later superseded by 3 µm, 2 µm, and 1.5 µm processes.

Industry[edit]

HP's NMOS II was a second generation nMOD process which was a shrink of their previous generation 7 µm nMOS also developed by HP's Loveland Division. The shrink was done in the hope they could double the speed while doubling density. Loveland went on on to create a third and final process, the NMOS III using a 1.5 µm process. While they succeeded in doubling the density and more than ten-folding the speed, the complexity of the chip still required them to fabricate it on 3 separate dies and package them together. Intel introduced their 2116 in 1976, the first 16 Kib DRAM which was also implemented using 5 micron design rules.

Foundry
Process Name
1st Production
WaferType
Size
TransistorTechnology
Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcellHigh-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcelleDRAM
IntelHP
 NMOS II
19761973
BulkBulk
51 mm51 mm
nMOSnMOS
PlanarPlanar
5 V5 V
1, 2
Value8 µm ΔValue7 µm Δ
5 µm0.63x5 µm0.71x
    
    
    
435 µm²0.34x  
    
    

5µm Microprocessors[edit]


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