Semiconductor & Computer Engineering
Semiconductor lithography processes technology
The 3 nanometer (3 nm or 30 Å) lithography process is a technology node semiconductor manufacturing
- process following the 5 nm process node.
Commercial integrated circuit manufacturing using 3 nm process is set to begin some time around 2023.
The term "3 nm" is simply a commercial name for a generation of a certain size and its technology, and
- does not represent any geometry of the transistor.
Contents
[hide]Industry[edit]
Intel[edit]
P1278 Intel's 5-nanometer (renamed as Intel 20A) process node is expected to ramp around the 2H 2024/2025 timeframe.
TSMC[edit]
N3 technology will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to
- 30% power reduction at the same speed as compared with N5 technology (According to TSMCs website).
If this holds true we could see 300+ MT/mm2.
Samsung[edit]
On May 24, 2017 Samsung announced they will be switching to a transistor they call Multi-Bridge-Channel FET
- (MBCFET), an extension of a Gate-all-around (GAA) FET.
This is planned for somewhere after the 5 nm node but the exact timeline or specification is currently unknown.
Specifications[edit]
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Intel | TSMC | TSMC | Samsung | ||||
|---|---|---|---|---|---|---|---|
| P1276 (CPU/Chipset) | N3(B) | N3E N3 Enhanced , N3P, N3X |
SF3E 3nm Gate All Around Early , SF3 3nm Gate All Around Plus
| ||||
| 2024 | 2023 | 2024, 2025, 2026 | 2024 | ||||
| EUV | EUV | EUV | EUV | ||||
| Yes | Yes | Yes | Yes | ||||
| SE EUV+DUV SAPQ | SALELE | SALELE | SALELE | ||||
| Bulk | Bulk | Bulk | Bulk | ||||
| 300 mm | 300 mm | 300 mm | 300 mm | ||||
| FinFET | FinFET | FinFET | GAAFET (MBCFET) | ||||
| Value | 4 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ | Value | 5 nm Δ |
| 30 nm | 1.0x | 23 nm | 0.82x | 23 nm | 0.82x | ||
| narrower | |||||||
| taller | |||||||
| 1.0x | |||||||
| 50 nm | 1.0x | 47 nm | 0.88x/0.92x | 48 nm | 0.94x | 48 nm | 1.0x |
| 30 nm | 1.0x | 23 nm | 0.82x | 23 nm | 0.82x | 28 nm | 1.0x |
| 0.0300 μm2 | 1.0x | ||||||
| 0.0240 μm2 | 1.0x | 0.0199 μm2 | 0.95x | 0.0210 μm2 | 1.0x | ||
| . | |||||||
3 nm process nodes[edit]
| Samsung [1][2] | TSMC [3][4][5] | Intel [6] | |||||
|---|---|---|---|---|---|---|---|
| Process name | 3GAE (SF3E) | 3GAP (SF3) | N3 (N3B) | N3E | N3P | N3X | Intel 3 |
| Transistor type | GAAFET (MBCFET) | FinFET | |||||
| Transistor density (MTr/mm2) |
150 | 190 | 197 | 216 | 224 | - | |
| Transistor gate pitch (nm) |
40 | - | 45 | 48 | - | - | 50 |
| Interconnect pitch (nm) |
32 | - | - | 23 | - | - | 30 |
| SRAM bit-cell size (μm2) |
- | - | 0.0199 | 0.021 | - | - | - |
| Release status | 2022 H1 risk production 2022 H2 production 2022 shipping |
2024 Q1 risk production 2024 H2 production |
2022 risk production 2023 production |
2024 |
2025 |
2026 |
2024 |
2 nm process nodes[edit]
| Samsung | TSMC | Intel | |||||||
|---|---|---|---|---|---|---|---|---|---|
| Process name | SF2 | SF2P | SF2X | SF2Z | N2 | N2P | N2X | 20A | 18A |
| Transistor type | MBCFET | GAAFET | RibbonFET | ||||||
| Transistor density (MTr/mm2) | 231 | - | - | - | 313 | - | - | - | 238 |
| Transistor gate pitch (nm) |
- | - | - | - | - | - | - | - | - |
| Interconnect pitch (nm) |
- | - | - | - | - | - | - | - | - |
| SRAM bit-cell size (μm2) |
- | - | - | - | 0.0175 μm² | - | - | - | 0.021 μm² |
| Release status | 2025 volume production | 2026 volume production | 2026 volume production | 2027 volume production | 2024 H2 risk production 2025 H2 volume production |
2026 H2 volume production |
2026 H2 volume production |
2024 H1 risk production 2024 volume production Canceled 2024 |
2024 H2 risk production 2025 H1 production |
3 nm Microprocessors[edit]
- Qualcomm
- Snapdragon 8 Elite
- MediaTek
- Dimensity 9400
This list is incomplete; you can help by expanding it.
3 nm Microarchitectures[edit]
4 nm Microarchitectures[edit]
This list is incomplete; you can help by expanding it.
References[edit]
- Kinam Kim, President of Semiconductor Business, announced MBCFET for the node after 5 nm, May 24, 2017