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    Cortex-A520 - Microarchitectures - ARM    
                	
														| Edit Values | |
| Cortex-A520 (Hayes) µarch | |
| General Info | |
| Arch Type | CPU | 
| Designer | ARM Holdings | 
| Manufacturer | TSMC | 
| Introduction | Q4 2023 | 
| Process | 4 nm | 
| Core Configs | 4 | 
| Pipeline | |
| Type | In-order | 
| OoOE | No | 
| Speculative | Yes | 
| Reg Renaming | No | 
| Decode | 3-way | 
| Instructions | |
| ISA | ARMv9.2-A | 
| Extensions | FPU, NEON, SVE, SVE2, TrustZone | 
| Cache | |
| L1I Cache | 32-64 KiB/core 4-way set associative  | 
| L1D Cache | 32-64 KiB/core 4-way set associative  | 
| L2 Cache | 0-512 KiB/cluster 4-way set associative  | 
| L3 Cache | 256 KiB-32 MiB (optional)  | 
| Succession | |
Cortex-A520 (Hayes) is a planned ultra-high efficiency Cortex microarchitecture being designed by ARM Holdings as a successor to the Cortex-A510 (Klein). Cortex-A520 is scheduled for introduction around the 2023 timeframe.
Contents
Process Technology[edit]
The Cortex-A520 was primarily designed to take advantage of TSMC's 4 nm (TSMC N4P).
Architecture[edit]
Key changes from Cortex-A510[edit]
- Update to ARMv9.2-A [1]
 - Support only 64-bit applications
 - Up to 512 KiB of private L2 cache (from 256 KiB)
 - 8% peak performance improvement over the Cortex-A510 [2]
 - Add QARMA3 Pointer Authentication (PAC) algorithm support
 
Comparison[edit]
| uArch | Cortex-A53 | Cortex-A55 | Cortex-A510 | Cortex-A520 | Cortex-A530 | 
|---|---|---|---|---|---|
| Codename | Apollo | Ananke | Klein | Hayes | Nevis | 
| Peak clock speed | 2.3 GHz | 2.1 GHz | 2.0 GHz | 2.0 GHz | |
| Architecture | ARMv8.0-A | ARMv8.2-A | ARMv9.0-A | ARMv9.2-A | |
| AArch | 32-bit and 64-bit | 64-bit | |||
| L1-I + L1-D | 8/64 + 8/64 KiB | 16/64 + 16/64 KiB | 32/64 + 32/64 KiB | ||
| L2 | 0–256 KiB | 0–512 KiB | |||
| L3 | ? | 0–4 MiB | 0–16 MiB | 0–32 MiB | |
| Decode Width | 2 | 3 | 3 (2 ALU) | ||
| Dispatch | 8 | ||||
Cortex-X/-A Core[edit]
| Year | Cortex-X Core | Cortex-A Core | 
|---|---|---|
| 2020 |  Cortex-X1 (Hera)  Cortex-X1C (Hera-C)  | 
 Cortex-A78 (Hercules)   Cortex-A78C (Hera Prime)  | 
| 2021 |  Cortex-X2  (Matterhorn-ELP)  | 
 Cortex-A710 (Matterhorn)  Cortex-A510 (Klein)  | 
| 2022 | Cortex-X3 (Makalu-ELP) | Cortex-A715 (Makalu) | 
| 2023 | Cortex-X4 (Hunter-ELP) |  Cortex-A720 (Hunter)  Cortex-A520 (Hayes)  | 
| 2024 |   Cortex-X925 (Blackhawk)  | 
 Cortex-A720AE (Hunter-AE)  Cortex-A725 (Chaberton)  | 
| 2025 | Cortex-X930 (Travis) |  Cortex-A730 (Gelas)  Cortex-A530 (Nevis)  | 
Processors[edit]
- Snapdragon 6 Gen 4 (SM6650) • 4nm (TSMC N4P)
 
- 1× @2.3GHz Kryo Prime (Cortex-A720) +
 - 3× @2.2GHz Kryo Gold (Cortex-A720) +
 - 4× @1.8GHz Kryo Silver (Cortex-A520)
 
- Snapdragon 7+ Gen 3 (SM7675-AB) • 4nm
 
- 1× 2.8 GHz Kryo Prime (Cortex-X4) +
 - 4× 2.6 GHz Kryo Gold (Cortex-A720) +
 - 3× 1.9 GHz Kryo Silver (Cortex-A520)
 
- Snapdragon 7s Gen 3 (SM7635) • 4nm
 
- 1× @2.5GHz Kryo Prime (Cortex-A720) +
 - 3× @2.4GHz Kryo Gold (Cortex-A720) +
 - 4× @1.8GHz Kryo Silver (Cortex-A520)
 
- Snapdragon 8 Gen 3 (SM8650-AB) • 4 nm (TSMC N4P)
 
- 1× @3.3GHz Kryo Prime (Cortex-X4) +
 - 3× @3.15GHz Kryo Gold (Cortex-A720) +
 - 2× @2.96GHz Kryo Gold (Cortex-A720) +
 - 2× @2.27GHz Kryo Silver (Cortex-A520)
 
- Snapdragon 8 Gen 3 (SM8650-AA)
 
- 1× @3.05GHz Kryo Prime (Cortex-X4) +
 - 5× @2.96GHz Kryo Gold (Cortex-A720) +
 - 2× @2.04GHz Kryo Silver (Cortex-A520) Q4 2024
 
- Snapdragon 8 Gen 3 for Galaxy (SM8650-AC)
 
- 1× @3.4GHz Kryo Prime (Cortex-X4) +
 - 3× @3.15GHz Kryo Gold (Cortex-A720) +
 - 2× @2.96GHz Kryo Gold (Cortex-A720) +
 - 2× @2.27GHz Kryo Silver (Cortex-A520)
 
- Snapdragon 8s Gen 3 (SM8635)
 
- 1× @3.0GHz Kryo Prime (Cortex-X4) +
 - 4× @2.8GHz Kryo Gold (Cortex-A720) +
 - 3× @2.0GHz Kryo Silver (Cortex-A520)
 
See also[edit]
Reference[edit]
Facts about "Cortex-A520 - Microarchitectures - ARM"
| codename | Cortex-A520 (Hayes) + | 
| core count | 4 + | 
| designer | ARM Holdings + | 
| first launched | April 2023 + | 
| full page name | arm holdings/microarchitectures/hayes + | 
| instance of | microarchitecture + | 
| instruction set architecture | ARMv9.2-A + | 
| manufacturer | TSMC + | 
| microarchitecture type | CPU + | 
| name | Cortex-A520 (Hayes) + | 
| process | 4 nm (0.004 μm, 4.0e-6 mm) + |