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Cortex-X2 (Matterhorn-ELP) - Microarchitectures - ARM
| Edit Values | |
| Cortex-X2 (Matterhorn-ELP) µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | 2021 |
| Process | 10 nm, 7 nm, 5 nm |
| Core Configs | 1, 2, 4, 6, 8, 10, 12 |
| Pipeline | |
| Type | Superscalar, Pipelined |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 288 |
| Decode | 5-way |
| Instructions | |
| ISA | ARMv9.0-A |
| Extensions | FPU, NEON |
| Cache | |
| L1I Cache | 64 KiB/core 4-way set associative |
| L1D Cache | 64 KiB/core 4-way set associative |
| L2 Cache | 1 MiB/core 8-way set associative |
| L3 Cache | 16 MiB/cluster 16-way set associative |
| Cores | |
| Core Names | Cortex-X2 |
| Succession | |
| Contemporary | |
| Cortex-A710 (Matterhorn) Cortex-A510 (Klein) | |
Cortex-X2 (Matterhorn-ELP) is the successor to the Cortex-X1 (Hera), a performance-enhanced version of the Cortex-A710 (Matterhorn), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.
Contents
[hide]Cortex-X[edit]
| Year | Cortex-X Core | Cortex-A Core |
|---|---|---|
| 2020 | Cortex-X1 (Hera) Cortex-X1C (Hera-C) |
Cortex-A78 (Hercules) Cortex-A78C (Hera Prime) |
| 2021 | Cortex-X2 (Matterhorn-ELP) |
Cortex-A710 (Matterhorn) Cortex-A510 (Klein) |
| 2022 | Cortex-X3 (Makalu-ELP) | Cortex-A715 (Makalu) |
| 2023 | Cortex-X4 (Hunter-ELP) | Cortex-A720 (Hunter) Cortex-A520 (Hayes) |
| 2024 | Cortex-X925 (Blackhawk) |
Cortex-A720AE (Hunter-AE) Cortex-A725 (Chaberton) |
| 2025 | Cortex-X930 (Travis) | Cortex-A730 (Gelas) Cortex-A530 (Nevis) |
Architecture[edit]
Key changes from Cortex-X1[edit]
The processor implements the following changes: [1]
- Instruction set ARMv9.0
- 10 cycle pipeline down from 11, created by reducing dispatch stage from 2 cycles to 1
- Reorder buffer (ROB) increased by 30% from 224 entries to 288
- dTLB increased by 20% from 40 entries to 48
- Bfloat16 data type support
- Support for Aarch32 removed
- SVE2 SIMD support
- DSU-110
- Up to 12 cores (up from 8 cores)
- Up to 16MB L3 cache (up from 8MB)
- CoreLink CI-700/NI-700: up to 32MB SLC
Performance claims:
- Comparing the Cortex-X2 [2] to the Cortex-X1 with the same process,
clock speed, and 4MB of L3 cache (also known as ISO-process):- 16% greater integer performance / IPC
- 100% greater ML performance
- 30% peak performance improvement over the Cortex-X1 in smartphones
- (3.3GHz, 1MB L2, 8MB L3)
- 40% faster than an Intel Core i5-1135G7 at 15W (3.5GHz, 1MB L2, 16MB L3)
Comparison[edit]
- "Prime" core
| Architecture | Cortex-A78 | Cortex-X1 | Cortex-X2 | Cortex-X3 | Cortex-X4 | Cortex-X925 | Cortex-X930 |
|---|---|---|---|---|---|---|---|
| Code name | Hercules | Hera | Matterhorn-ELP | Makalu-ELP | Hunter-ELP | Blackhawk | Travis |
| ISA | ARMv8.2-A | ARMv9.0-A | ARMv9.2-A | ||||
| Peak clock speed | ~3.0 GHz | ~3.3 GHz | ~3.4 GHz | ~3.8 GHz | ~4.2 GHz | ||
| Max in-flight | 2x 160 | 2x 224 | 2x 288 | 2x 320 | 2x 384 | 2x 768 | |
| L0 (Mops entries) | 1536 [3] | 3072 | 1536 | 0 | |||
| L1-I + L1-D | 32+32 KiB | 64+64 KiB | 64+64 KiB | 64+64 KiB | |||
| L2 | 128–512 KiB | 0.25–1 MiB | 0.5–2 MiB | 2–3 MiB | |||
| L3 | 0–8 MiB [4] | 0–16 MiB | 0–32 MiB | ||||
| Decode width | 4 | 5 | 6 | 10 [5] | 10 | ||
| Dispatch | 6/cycle | 8/cycle | 10/cycle | ||||
References[edit]
- Jump up ↑ WikiChip Fuse (2021-05-25). Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2.
- Jump up ↑ Arm Announces Mobile Armv9 CPU Microarchitectures: Cortex-X2, Cortex-A710 & Cortex-A510.
- Jump up ↑ Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence.
- Jump up ↑ Schor, David (2020-05-26). Arm Cortex-X1: The First From The Cortex-X Custom Program.
- Jump up ↑ (2023-05-29) Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive.
Facts about "Cortex-X2 (Matterhorn-ELP) - Microarchitectures - ARM"
| codename | Cortex-X2 (Matterhorn-ELP) + |
| core count | 1 +, 2 +, 4 +, 6 +, 8 +, 10 + and 12 + |
| designer | ARM Holdings + |
| first launched | 2021 + |
| full page name | arm holdings/microarchitectures/cortex-x2 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv9.0-A + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-X2 (Matterhorn-ELP) + |
| pipeline stages | 288 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |