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From WikiChip
Chaberton - Microarchitectures - ARM
| Edit Values | |
| Chaberton µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | 2024 |
| Process | 7 nm, 5 nm |
| Core Configs | 1, 2, 4 |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Succession | |
Chaberton is the successor to Hunter, a low-power high-performance synthesizable ARM microarchitecture designed by ARM for the mobile market.
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/microarchitectures/chaberton&oldid=100276"
Facts about "Chaberton - Microarchitectures - ARM"
| codename | Chaberton + |
| core count | 1 +, 2 + and 4 + |
| designer | ARM Holdings + |
| first launched | 2024 + |
| full page name | arm holdings/microarchitectures/chaberton + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Chaberton + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |