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150 nm lithography process

The 150 nanometer (150 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 180 nm and 130 nm processes. Commercial integrated circuit manufacturing using 55 nm process began in early 2000s. This technology superseded by commercial 130 nm, 110 nm, and 90 nm processes.


On December 16, 1999, Samsung announced the development of a $1.8B Line 10, a 1M meter² site in Hwasung-gun, Kyonggi Province. Line 10 was dedicated for the production of 128 MiB, 256 MiB and Rambus DRAMs on a 150 nm process. Line 10 opened in the third quarter of 2000 producing 16,000 200 mm wafers per month going into full capacity in the in the first quarter of 2001 producing 32,000 wafers a month.

Process Name​
1st Production​
Metal Layers​
Contacted Gate Pitch​
Interconnect Pitch (M1P)​
SRAM bit cell
TSMC Fujitsu Samsung
2000 2002 2002
Value 180 nm Δ Value 180 nm Δ Value 180 nm Δ
 ? nm  ?x  ? nm  ?x  ? nm  ?x
 ? nm  ?x  ? nm  ?x  ? nm  ?x
3.42 µm2 0.74x  ? µm2  ?x  ? µm2  ?x

150 nm Microprocessors[edit]

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150 nm microarchitectures[edit]