From WikiChip
28 nm lithography process

The 28 nanometer (28 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 32 nm and 22 nm processes. Commercial integrated circuit manufacturing using 28 nm process began in 2011. This technology superseded by commercial 22 nm process.


Process Name
1st Production
Lithography Lithography
Wafer Type
Transistor Type
Metal Layers
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM bitcell High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM bitcell eDRAM
TSMC Common Platform Alliance UMC
28LP, 28HPL, 28HP 28LP, 28LPP, 28SLP 28HPC, 28HLP, 28HPC+, 28µLP
4Q 2011 2014 2013
193 nm 193 nm 193 nm
Yes Yes Yes
Bulk Bulk Bulk
300 mm 300 mm 300 mm
Planar Planar Planar
1 V, 0.8 V 1 V, 0.85 V 0.9 V, 1.05 V, 0.7 V
10 10 10
Value 32 nm Δ Value 32 nm Δ Value 40 nm Δ
24 nm   28 nm   33 nm  
117 nm   113.4 nm   120 nm  
90 nm   90 nm   90 nm  
    0.152 µm²      
0.127 µm²   0.120 µm²   0.124 µm²  
0.155 µm²   0.197 µm²      

28 nm Microprocessors[edit]

This list is incomplete; you can help by expanding it.

28 nm Microarchitectures[edit]

This list is incomplete; you can help by expanding it.


  • Samsung foundry solution for 32 & 28 nm
  • Wu, Shien-Yang, et al. "A highly manufacturable 28nm cmos low power platform technology with fully functional 64mb sram using dual/tripe gate oxide process." VLSI Technology, 2009 Symposium on. IEEE, 2009.
  • Shang, Huiling, et al. "High performance bulk planar 20nm CMOS technology for low power mobile applications." VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.
  • Arnaud, F., et al. "Competitive and cost effective high-k based 28nm CMOS technology for low power applications." Electron Devices Meeting (IEDM), 2009 IEEE International. IEEE, 2009.
  • Yuan, J., et al. "Performance elements for 28nm gate length bulk devices with gate first high-k metal gate." Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on. IEEE, 2010.
  • Liang, C. W., et al. "A 28nm poly/SiON CMOS technology for low-power SoC applications." VLSI Technology (VLSIT), 2011 Symposium on. IEEE, 2011.
  • James, Dick. "High-k/metal gates in the 2010s." Advanced Semiconductor Manufacturing Conference (ASMC), 2014 25th Annual SEMI. IEEE, 2014.