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Lake Crest - Microarchitectures - Intel Nervana
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Lake Crest µarch
General Info
Arch TypeNPU
IntroductionNovember 17, 2016
Process28 nm

Lake Crest is a neural processor microarchitecture designed by Nervana.

Process Technology[edit]

Lake Crest is fabricated on TSMC's 28 nm process.


Lake Crest was designed from the ground up for deep learning. The architecture itself is a tensor-based architecture, meaning it's optimized for blocks of compute instead of operating on scalars (as would a traditional Intel CPU would).

  • Tensor-based architecture
    • Nervana Engine
  • Flexpoint number format
  • No caches
    • Software explicitly manages all on-chip memory
  • HBM2 memory
    • 32 GiB of in-package memory
    • 8 Tbit/s bandwidth
  • 12 x Inter-Chip Links (ICL)
    • bi-directional high-bandwidth direct chip-to-chip interconnect
    • 100 GB/s (1,200 GB/s aggregate)

This list is incomplete; you can help by expanding it.

Block Diagram[edit]


knights crest chip block diagram.svg

Processing Cluster[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

  • 32 GiB on-package HBM2
    • 1 TiB/s


Nervana stated that Lake Crest is "near-reticle size" implying the die size is likely around the 650-750 mm².

Additional Shots[edit]


  • Rao, N. (2016, November). Pathfinding and Hardware Deep Dive. 2016 AI Day, San Francisco.
  • Rao, N. (2018, May). Keynote presentation. 2018 AI DevCon, San Francisco.
codenameLake Crest +
designerNervana +
first launchedNovember 17, 2016 +
full page namenervana/microarchitectures/lake crest +
instance ofmicroarchitecture +
manufacturerTSMC +
nameLake Crest +
process28 nm (0.028 μm, 2.8e-5 mm) +