|Lake Crest µarch|
|Introduction||November 17, 2016|
Lake Crest was designed from the ground up for deep learning. The architecture itself is a tensor-based architecture, meaning it's optimized for blocks of compute instead of operating on scalars (as would a traditional Intel CPU would).
- Tensor-based architecture
- Nervana Engine
- Flexpoint number format
- No caches
- Software explicitly manages all on-chip memory
- HBM2 memory
- 32 GiB of in-package memory
- 8 Tbit/s bandwidth
- 12 x Inter-Chip Links (ICL)
- bi-directional high-bandwidth direct chip-to-chip interconnect
- 100 GB/s (1,200 GB/s aggregate)
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- 32 GiB on-package HBM2
- 1 TiB/s
Nervana stated that Lake Crest is "near-reticle size" implying the die size is likely around the 650-750 mm².
- TSMC 28 nm process
- 650-750 mm² die size
- Rao, N. (2016, November). Pathfinding and Hardware Deep Dive. 2016 AI Day, San Francisco.
- Rao, N. (2018, May). Keynote presentation. 2018 AI DevCon, San Francisco.