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Vector Carry-Less Multiplication of Quadwords (VPCLMULQDQ) - x86
x86
Instruction Set Architecture
Instruction Set Architecture
General
Variants
Topics
- Instructions
- Addressing Modes
- Registers
- Model-Specific Register
- Assembly
- Interrupts
- Micro-Ops
- Timer
- Calling Convention
- Microarchitectures
- CPUID
CPUIDs
Modes
Extensions(all)
Vector Carry-Less Multiplication of Quadwords (VPCLMULQDQ) is an x86 extension.
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Contents
Overview[edit]
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VPCLMULQDQ - ...
Motivation[edit]
Detection[edit]
The VPCLMULQDQ feature flag indicates support for the AVX variant of this instruction operating on 256-bit vectors.
The AVX-512 variant with EVEX encoding operating on 512-bit vectors is supported if the VPCLMULQDQ and AVX512F (Foundation) flags are set. The 128- and 256-bit versions with EVEX encoding are supported if the AVX512VL (Vector Length) flag is set as well.
The earlier PCLMULQDQ extension provides SSE and AVX variants of this instruction operating on 128-bit vectors.
| CPUID | Instruction Set | |
|---|---|---|
| Input | Output | |
| EAX=07H, ECX=0 | ECX[bit 10] | VPCLMULQDQ |
| EAX=07H, ECX=0 | EBX[bit 16] | AVX512F |
| EAX=07H, ECX=0 | EBX[bit 31] | AVX512VL |
Microarchitecture support[edit]
| Designer | Microarchitecture | Year | Support Level | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VPCLMULQDQ AVX |
VPCLMULQDQ AVX-512 (128/256) |
VPCLMULQDQ AVX-512 (512) | |||||||||||||||||||
| Intel | Ice Lake (server) | 2021 | ✔ | ✔ | ✔ | ||||||||||||||||
| AMD | Zen 3 | 2020 | ✔ | ✘ | ✘ | ||||||||||||||||
| Zen 4 | 2022 | ✔ | ✔ | ✔ | |||||||||||||||||
Intrinsic functions[edit]
__m256i _mm256_clmulepi64_epi128(__m256i, __m256i, const int);
__m512i _mm512_clmulepi64_epi128(__m512i, __m512i, const int);