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Macro-Operation Fusion (MOP Fusion)

Not to be confused with micro-operation fusion.

Macro-Operation Fusion (also Macro-Op Fusion, MOP Fusion, or Macrofusion) is a hardware optimization technique found in Intel's x86 microarchitectures whereby a pair of adjacent macro-operations are merged into a single macro-operation prior to decoding. Those instructions are later decoded into fused-µOPs.


The technique for fusing instructions is owned by Intel and is protected by Patent US6675376 ("System and method for fusing instructions") originally filed in December 2000. MOP Fusion was first introduced in 2006 in the Core microarchitecture and has been featured in every Intel microarch since.


A fused instruction remains fused throughout its lifetime. Therefore fused instructions can represent more work with less bits, free up execution units, tracking information (e.g. in the rename unit), save pipeline bandwidth in all stages from decode to retire, and consequently save power. Note that this is done before decoding, therefore even decoding bandwidth is saved.

Conditional branching are a very common operation in almost all workloads; by Intel estimates it makes up 15% of all instructions. Macro-op fusion also helps workloads that are not compiled such as in the case of many interpreted programming languages (e.g. PHP, the software running WikiChip).


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Slides from Intel's Core microarchitecture presentation.

After the boundaries of macro-ops are found and marked, they are delivered to the instruction queue before being fed to the decoders. At that stage of the pipeline, macro-operation fusion opportunities can be identified and exploited.

A pair of two dependent instructions are first compared against a set of criteria. For example, either the first source or destination operand must be a register and the second source operand (if one exists) must be an immediate value or a non-RIP-relative memory. Fusion replaces the two instructions with a single instruction representing both operations behaviorally.

Fusion is done on compare flag-modifying instruction (e.g., CMP or ADD) with a subsequent conditional jump instruction. The produced output is a single single operation-and-branch instruction. The final fused instruction remains as such for its remaining lifetime; that is the fused instruction will stay fused throughout the pipeline until execution units where it may be executed on a single port or dual-issued on two appropriate ports.

  • Two instructions must be right next to each other, with no other instruction in between
  • First instruction must be one of the following: CMP, TEST, ADD, SUB, INC, DEC, or AND.
  • Second instruction must be a conditional jump (e.g., JA, JAE, JE, JNE)
  • Fusion cannot take place if the first instruction ends on byte 63 of a cache line and the second instruction starts at byte 0 of the next line.

Additionally, only up to 1 macrofusion can take place each cycle. If there it's possible to perform 2 macrofusions, only the first pair will be fused. The second pair will continue unfused.


Prior limitations[edit]

Nehalem µarch limitations[edit]

In Nehalem, Intel introduced a number of enhancements:

Core µarch limitations[edit]

The original implementation in the Core microarchitecture was much more limited than in recent processors.

  • First instruction must be one of the following: CMP and TEST
  • Macro Fusion is restricted to 16-bit and 32-bit mode only (including 32-bit compatibility sub-mode in x86-64).
  • CMP and TEST can fuse when comparing:
    • REG-REG. (e.g, CMP EAX,ECX; JZ label)
    • REG-IMM. (e.g., CMP EAX,0x80; JZ label)
    • REG-MEM. (e.g., CMP EAX,[ECX]; JZ label)
    • MEM-REG. (e.g., CMP [EAX],ECX; JZ label)
  • CMP and TEST can not be fused when comparing MEM-IMM (e.g. CMP [EAX],0x80; JZ label)
  • TEST can fused with all conditional jumps
  • CMP can only be fused with Carry Flag (CF) / Zero Flag (ZF) conditional jumps: JA, JNBE, JAE, JNB, JNC, JE, JZ, JNA, JBE, JNAE, JC, JB, JNE, JNZ

See also[edit]