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Talk:10 nm lithography process

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What is the source for interconnect and gate pitches?[edit]

What are the sources for the pitches of TSMC and Samsung. For Intel, what is the source of the interconnect pitch because Intel hasn't disclosed that one. Only gate pitch ( — Preceding unsigned comment added by (talkcontribs)

To be clear Intel hasn't "formally" disclose any values. The Pitch and Gate are initial values given by Mark Bohr during one of his presentations. Wish I could actually link to anything, but these slides are not online anywhere. The TSMC/Samsung ones I believe someone gave me initial values, but I'll need to double check. Just glancing off the dates (first week of February this year), these values might have come from ISSCC 2016 (ieee international solid-state circuits conference). But I'd need to double check that.
That being said, all the values will need to be double checked and possibly updated once the foundries formally announce their processes. --David (talk) 11:51, 3 September 2016 (EDT)
I added a 'Preliminary Data' template to the article make it clear. --At32Hz (talk) 14:45, 3 September 2016 (EDT)
To be clear, the value of the gate pitch was 55nm before I changed it to the publicly disclosed value of 54nm (see link). So are you sure your information is accurate? — Preceding unsigned comment added by Witeken (talkcontribs)
If you think they're inaccurate, feel free to change them back to "?" until we get more verifiable numbers. --At32Hz (talk) 17:20, 5 September 2016 (EDT)
I went ahead and cleared the values until they are published online. --At32Hz (talk) 17:42, 5 September 2016 (EDT)
Pfft, looks like my numbers were correct. Intel announced their 10nm today. 54 nm x 36 nm. I'm starting to think I might have not supposed to disclose those numbers back then TBH. --David (talk) 16:26, 28 March 2017 (EDT)