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User talk:At32Hz

Use of Ivy Bridge block diagram for my paper[edit]

Hi there, Is it possible to change the licensing of the above mentioned diagram, so I can use it in my upcoming paper, citing you and WikiChips? Your help would be greatly appreciated. mossaiby (remove this) yahoo (well, this one too) com

Use of Broadwell block diagram for dissertation[edit]

Hey At32Hz, I'm writing my dissertation on a particular optimization for group prefetching, and ran my experiments on a Xeon E5-2630 v4. Could I include your Broadwell block diagram svg ( in my dissertation? The dissertation will be freely available to the public, and your diagram would be attributed to you, with a link to WikiChip included. Tried to create a WikiChip account, but was not able to do so. theod AT


Use of skylake_block_diagram.svg for my free eBook[edit]

Hi, is there any chance I could have your explicit permission to use skylake_block_diagram: image for my free pdf book (it will be published under Creative Commons license). More info about the book here. Thanks!


UPD: At32Hz, ping. For some reason, I cannot create an account, so sorry for the anonymous writing.

Use of Ryzen .svg for Wikipedia article[edit]

Hiya, I was just wondering if I could have your explicit permission to use this: image for the Ryzen wikipedia page found here: for the main image. Thanks! Cautilus (talk) 05:16, 10 February 2018 (EST)

License was changed to "CC BY-SA 3.0". But you might want to use the official "Ryzen" logo for the infobox on there.
--At32Hz (talk) 06:46, 10 February 2018 (EST)


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Re "Goldmont" article. You stuffed all my edits under "latency", even though most of them are about throughput. Throughput != latency. — Preceding unsigned comment added by (talkcontribs)

Yup my bad. It should've been throughput. I've changed it accordingly. --At32Hz (talk) 09:51, 27 October 2016 (EDT)

14 nm[edit]

"14nm lithography article" You reverted my edit about the sram density, while the Intel slide in the article clearly states that the sram density is higher than that of a logic tall cell. So do you claim the slide is wrong, or do i miss something obvious? — Preceding unsigned comment added by Nible (talkcontribs) 09:20, Jun 17, 2005 (UTC)

Yea my mistake, I reverted it. I was going through new 14/7nm process info and mixed up some stuff. My bad. --At32Hz (talk) 18:01, 20 July 2017 (EDT)

Intel SoC diagrams[edit]

Hey, can you switch the Intel diagrams to correctly correspond to how the cache layout changes in Skylake & Kaby? As they shifted to the sides.--David (talk) 23:24, 7 September 2017 (EDT)

Also Sandy Bridge could use one such diagram as well! --David (talk) 23:25, 7 September 2017 (EDT)
Sure thing! --At32Hz (talk) 23:11, 8 September 2017 (EDT)

Please update non-AVX frequencies for 6146[edit]

I'm not at liberty to share the information, but I have an Intel document with frequencies for the Intel Xeon Gold 6146 processor. They differ from what is at intel/xeon_gold/6146#Frequencies. Discrepancies are for some of the non-AVX frequencies; my data for both sets of AVX frequencies are the same as yours. From the edit history for that page, it appears that you entered those frequencies. Would you please check your sources and update the frequencies as appropriate? Thanks! — Preceding unsigned comment added by ChuckEdN (talkcontribs)

Hey Chuck,
I follow the published frequencies from Intel's own datasheet, you can find them here. I screenshot the appropriate row for the 6146 here
That says the frequencies are "4.2, 4.2, 4.1, 4.1, 4.0, 4.0, 4.0, 4.0, 3.9, 3.9, 3.9, 3.9". which are the same ones we have for the Xeon Gold 6146. Are you saying those values are wrong? --At32Hz (talk) 13:18, 15 September 2017 (EDT)

Chuck says: Sure enough, there's a discrepancy between the Intel site you cited and the Intel documentation I have. I'll see what I can find out and get back here. — Preceding unsigned comment added by ChuckEdN (talkcontribs)