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Changes related to "5 nm lithography process"
← 5 nm lithography process

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Show new changes starting from 06:12, 22 June 2025
   
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21 June 2025

     12:33  3 nm lithography process‎ (diff | hist) . . (+1,745)‎ . . 2a10:484:3:1::12 (talk) (updated 3nm data with confrence paper data, actual dates, and high level teardown information)
     11:19  10 nm lithography process‎‎ (2 changes | history) . . (+208)‎ . . [2a10:484:3:1::12‎ (2×)]
     11:17  7 nm lithography process‎ (diff | hist) . . (-110)‎ . . 2a10:484:3:1::12 (talk) (corrected dates and cleared up some wording for the intel 7 section. Also corrected SMIC 7nm to be DUV not EUV. Could not correct the 7nm comp table to DUV and P1274 though since it is inaccessable.)
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