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Kirin 980 - HiSilicon
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Kirin 980
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model Number980
MarketMobile
IntroductionAugust 31, 2018 (announced)
August 31, 2018 (launched)
General Specs
FamilyKirin
Frequency2,600 MHz, 1,920 MHz, 1,800 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A76, Cortex-A55
Core NameCortex-A76, Cortex-A55
Process7 nm
Transistors6,900,000,000
TechnologyCMOS
Word Size64 bit
Cores8
Threads8

Kirin 980 is a 64-bit high-performance mobile ARM LTE SoC designed by HiSilicon and introduced in late 2018. Fabricated on TSMC's 7 nm process, the 980 incorporates four big Cortex-A76 cores operating at up to 2.6 GHz along with four little Cortex-A55 cores operating at up to 1.8 GHz. This SoC has an LTE modem supporting 1.4 Gbps download (Cat21), incorporates an ARM Mali-G76, and supports LPDDR4X-4266 memory.

Overview[edit]

Introduced at the 2018 IFA, the overall core organization has changed from the Kirin 970 which was introduced the previous year. The 980 features two high-performance big Cortex-A76 core operating at 2.6 GHz, 2 medium-performance big Cortex-A76 operating at 1.92 GHz, and four little Cortex-A55 cores operating at 1.8 GHz. Compard to the 970, the 980 features 40% power efficiency and 62.5% smaller die area due to the process shrink. The 980 ballooned to over 25% more transistors from 5.5 billion in the 970 to 6.9 billion. The 980 adds many enhancements, including a more powerful Mali G76 GPU and incorporates a new dual-neural processor designed for AI acceleration. The 970 has two improved ISPs and a more powerful LTE modem supporting up to User Equipment (UE) category 21 capable of reaching a maximum downlink of 1.4 Gbps.

Cache[edit]

Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache


For the Cortex-A76:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
L1I$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
4x64 KiB  
L1D$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
4x64 KiB  

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  4x512 KiB  

For the Cortex-A55:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
L1I$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB  
L1D$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
4x32 KiB  

L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  4x128 KiB  


Memory controller[edit]

The Kirin 980 supports 4-channel LPDDR4X up to 2133 MHz. Each channel supports at most two ranks.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4266
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels4
Width16 bit
Max Bandwidth31.78 GiB/s
Bandwidth
Double 15.89 GiB/s
Quad 31.78 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G76
DesignerARM Holdings
Execution Units10Max Displays2
Frequency750 MHz
0.75 GHz
750,000 KHz
OutputDSI

Standards
DirectX12
OpenCL1.2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0

Wireless[edit]

  • LTE Modem
    • DL: Up to User Equipment (UE) category 21
      • Downlink of up to 1.4 Gbps (4x4 MIMO + 256QAM 3CC CA = 1.2 Gbps, 2x2 MIMI + 256QAM + 1CC = 200 Mbps)
    • UL: Up to User Equipment (UE) category 18
      • Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
  • Wi-Fi 802.11 ac
  • Bluetooth 5
  • NFC
  • GPS / A-GPS / GLONASS / BDS

Bibliography[edit]

  • Huawei Kirin 980 Keynote, 2018 IFA
Facts about "Kirin 980 - HiSilicon"
base frequency2,600 MHz (2.6 GHz, 2,600,000 kHz) +, 1,920 MHz (1.92 GHz, 1,920,000 kHz) + and 1,800 MHz (1.8 GHz, 1,800,000 kHz) +
core count8 +
core nameCortex-A76 + and Cortex-A55 +
designerHiSilicon + and ARM Holdings +
familyKirin +
first announcedAugust 31, 2018 +
first launchedAugust 31, 2018 +
full page namehisilicon/kirin/980 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuMali-G76 +
integrated gpu base frequency750 MHz (0.75 GHz, 750,000 KHz) +
integrated gpu designerARM Holdings +
isaARMv8 +
isa familyARM +
l1$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + and 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l1d$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + and 0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l1i$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + and 0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldate3000 +
manufacturerTSMC +
market segmentMobile +
max memory channels4 +
microarchitectureCortex-A76 + and Cortex-A55 +
model number980 +
nameKirin 980 +
process7 nm (0.007 μm, 7.0e-6 mm) +
supported memory typeLPDDR4X-4266 +
technologyCMOS +
thread count8 +
transistor count6,900,000,000 +
word size64 bit (8 octets, 16 nibbles) +