Edit Values
Exynos 990
General Info
Designer	Samsung, ARM Holdings
Manufacturer	Samsung
Model Number	990
Part Number	S5E9830
Market	Mobile
Introduction	October 23, 2019 (announced) 2020 (launched)
General Specs
Family	Exynos
Series	Exynos 9
Frequency	3.0 GHz, 2.6 GHz, 2.1 GHz
Microarchitecture
ISA	ARMv8.2 (ARM)
Microarchitecture	Mongoose 5, Cortex-A76, Cortex-A55
Core Name	Mongoose 5, Cortex-A76, Cortex-A55
Process	7 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
Max Memory	16 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
Vcore	1.13 V-1.20 V
TDP	8 W
cTDP down	8 W
cTDP down frequency	2.73 GHz
cTDP up	15 W
cTDP up frequency	3.016 GHz
Tjunction	95 °C – 115 °C
Succession
Exynos 9825

Exynos 990 (S5E9830) is a 64-bit octa-core ARM high performance mobile SoC designed by Samsung and introduced in 2020.

The processor is fabricated on Samsung's 7 nm FinFET (EUV) process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose 5 big cores, 2 Cortex-A76 middle cores, and 4 Cortex-A55 little cores. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR5-5500 memory and incorporates a Mali-G77 MP11 GPU. The 990 is designed to go along with Exynos Modem 5123 5G modem.

Features

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

[Edit/Modify Supported Features]

	Supported ARM Extensions & Processor Features
	NEON Advanced SIMD extension CRC32 CRC-32 checksum Extension Crypto Cryptographic Extension FP Floating-point Extension

ISP

• 108MP Rear
• 24.8MP Front
• 24.8MP + 24.8MP Dual

NPU

The Exynos 990 features Samsung's homegrown NPU. The new NPU features two execution cores (+ DSP).

The new NPU is capable of a peaking compute of fifteen trillion operations per second (TOPs).

Cache

Main articles: Mongoose 5 § Cache and Cortex-A76 § Cache

For the Mongoose 5 core cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 192 KiB 196,608 B 0.188 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 4-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 8-way set associative   L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     2x512 KiB 16-way set associative   L3$ 2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB     2x1 MiB

For the Cortex-A76 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB 16-way set associative   L2$ 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB     2x256 KiB 8-way set associative

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR5-5500 Supports ECC No Max Mem 12 GiB Frequency 2750 MHz Controllers 4 Channels 4 Width 16 bit Max Bandwidth 44 GB/s 40.978 GiB/s 41,961.67 MiB/s 44,000 MB/s 0.04 TiB/s 0.044 TB/s Bandwidth Single 11 GiB/s Double 22 GiB/s Quad 44 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G77 Designer ARM Holdings Execution Units 11 Max Displays 2 Frequency 832 MHz 0.832 GHz 832,000 KHz Output DSI Standards DirectX 12 OpenCL 2 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

Codec	Encode	Decode
HEVC (H.265)	✔	✔
MPEG-4 AVC (H.264)	✔	✔
VP9	✔	✔

All at 4K UHD 150fps.

Utilizing devices

• Samsung Galaxy S20 Series
• Samsung Galaxy Note 20 Series

This list is incomplete; you can help by expanding it.