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Kirin 810 - HiSilicon
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Kirin 810
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model Number810
MarketMobile
IntroductionJune 21, 2019 (announced)
June 21, 2019 (launched)
General Specs
FamilyKirin
Series800
Frequency2,270 MHz, 1,880 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A76, Cortex-A55
Core NameCortex-A76, Cortex-A55
Process7 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max CPUs1 (Uniprocessor)
Succession
k810.jpg

Kirin 810 is a 64-bit octa-core mid-range performance mobile ARM SoC introduced by HiSilicon in mid-2019. This chip, which is fabricated on TSMC's 7 nm process, features two Cortex-A76 big cores operating at up to 2.27 GHz along with six Cortex-A55 little cores operating at up to 1.88 GHz. The 810 incorporates ARM's Mali-G52 MP6 GPU.

Cache[edit]

Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache


For the Cortex-A76:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
L1I$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
2x64 KiB  
L1D$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
2x64 KiB  

L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x512 KiB  

For the Cortex-A55:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
0.375 MiB
393,216 B
3.662109e-4 GiB
L1I$192 KiB
0.188 MiB
196,608 B
1.831055e-4 GiB
6x32 KiB  
L1D$192 KiB
0.188 MiB
196,608 B
1.831055e-4 GiB
6x32 KiB  

L2$768 KiB
0.75 MiB
786,432 B
7.324219e-4 GiB
  6x128 KiB  


Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4266
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels4
Width16 bit
Max Bandwidth31.78 GiB/s
Bandwidth
Double 15.89 GiB/s
Quad 31.78 GiB/s


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G52
DesignerARM Holdings
Execution Units6Max Displays2
Frequency850 MHz
0.85 GHz
850,000 KHz
Output

Max Resolution
 2340x1080

Standards
DirectX12
OpenCL2.0
OpenGL ES3.2
OpenVG1.1
Vulkan1.0
  • Hardware Acceleration
    • Decode: 1080p @ 60fps
    • Encode: 1080p @ 30fps

NPU[edit]

This is the first neural processing unit to use their own homegrown NPU based on Hisilicon's first generation Da Vinci architecture. The NPU contains one processor core and a scheduling core.

ISP[edit]

  • 40 MP+ 24 MP dual

48 single

Wireless[edit]

  • LTE Modem
    • DL: Up to User Equipment (UE) category 21
      • Downlink of up to 1.4 Gbps (4x4 MIMO + 256QAM 3CC CA = 1.2 Gbps, 2x2 MIMI + 256QAM + 1CC = 200 Mbps)
    • UL: Up to User Equipment (UE) category 18
      • Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
  • Wi-Fi 802.11 ac
  • Bluetooth 5
  • NFC
  • GPS / A-GPS / GLONASS / BDS

Location[edit]

  • GPS, AGPS, Glonass, Beidou

Utilizing devices[edit]

  • Huawei Nova 5
  • Huawai 9X Pro, 9X

This list is incomplete; you can help by expanding it.

Facts about "Kirin 810 - HiSilicon"
base frequency2,270 MHz (2.27 GHz, 2,270,000 kHz) + and 1,880 MHz (1.88 GHz, 1,880,000 kHz) +
core count8 +
core nameCortex-A76 + and Cortex-A55 +
designerHiSilicon + and ARM Holdings +
familyKirin +
first announcedJune 21, 2019 +
first launchedJune 21, 2019 +
full page namehisilicon/kirin/810 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuMali-G52 +
integrated gpu base frequency850 MHz (0.85 GHz, 850,000 KHz) +
integrated gpu designerARM Holdings +
isaARMv8 +
isa familyARM +
l1$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + and 0.375 MiB (384 KiB, 393,216 B, 3.662109e-4 GiB) +
l1d$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) + and 0.188 MiB (192 KiB, 196,608 B, 1.831055e-4 GiB) +
l1i$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) + and 0.188 MiB (192 KiB, 196,608 B, 1.831055e-4 GiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
ldateJune 21, 2019 +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory channels4 +
microarchitectureCortex-A76 + and Cortex-A55 +
model number810 +
nameKirin 810 +
process7 nm (0.007 μm, 7.0e-6 mm) +
series800 +
supported memory typeLPDDR4X-4266 +
technologyCMOS +
thread count8 +
used byHuawei Nova 5 + and Huawai 9X Pro, 9X +
word size64 bit (8 octets, 16 nibbles) +