|EPYC Embedded 3451|
|Introduction||February 21, 2018 (announced)|
February 21, 2018 (launched)
|Turbo Frequency||3,000 MHz (1 core),|
2,450 MHz (16 cores)
|Core Name||Snowy Owl|
|MCP||Yes (2 dies)|
|Word Size||64 bit|
|Max CPUs||1 (Uniprocessor)|
|Max Memory||1 TiB|
|Tjunction||0 °C – 95 °C|
EPYC Embedded 3451 is a 64-bit hexadeca-core x86 embedded microprocessor introduced by AMD in early 2018 for dense servers and edge devices. Fabricated on a 14 nm process based on the Zen microarchitecture, this chip operates at 2.15 GHz with a TDP of 100 W and a turbo frequency of up to 3 GHz. The 3451 supports up to 1 TiB of quad-channel DDR4-2666 memory.
- Main article: Zen § Cache
[Edit/Modify Cache Info]
is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU
by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.
The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.
Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.
Note: All units are in kibibytes
|16x64 KiB||4-way set associative|| |
|16x32 KiB||8-way set associative||write-back|
| || ||16x512 KiB||8-way set associative||write-back|
| || ||4x8 MiB||16-way set associative||write-back|
[Edit/Modify Memory Info]
Integrated Memory Controller
|Max Mem||1 TiB|
|Max Bandwidth||79.47 GiB/s|
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
| [Edit] Memory Configurations
| Quad Channel
|| Single Rank
|| 1 DIMM
| 2 DIMMs
| Double Rank
|| 1 DIMM
| 2 DIMMs
The EPYC Embedded 3451 has 64 PCIe lanes that are MUX'ed with a number of other ports and can be reconfigured as either SATA ports (up to 16 such ports), or as GbE ports (up to 10 such ports), or any mixed configuration of those options.