|Designer||University of Michigan, University of Washington, Cornell University, University of California|
Celerity is a custom RISC-V-based neural processor microarchitecture. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego.
Celerity means 'swiftness of movement' which is the intended purpose of the architecture.
Celerity is a university-based research chip designed for the acceleration of artificial intelligence. The design and implementation of the chip was said to have taken just nine months through the use of agile development and leveraging existing open-source code. The design is intended to allow enough flexibility as AI workloads continue to evolve. Designed for TSMC 16 nm process, the chip integrates three separate tiers of architectures, each is progressively more specialized, less flexible, but more power-efficient. The first tier, the general-purpose tier, integrates five powerful RISC-V Rocket cores capable of running an operating system and managing the rest of the SoC. The second tier, the massively parallel tier, integrates a massive array of 496 parallel highly-efficient, but simple, RISC-V Vanilla-5 cores. The last tier is the specialization tier which integrates a specialized custom BNN accelerator.
Massively parallel tier
- 2019 Symposia on VLSI Technology and Circuits (VLSI 2019).
- IEEE Hot Chips 29 Symposium (HCS) 2017.
|designer||University of Michigan +, University of Washington +, Cornell University + and University of California +|
|full page name||umich/microarchitectures/celerity +|
|instance of||microarchitecture +|
|instruction set architecture||RISC-V +|
|microarchitecture type||CPU +|
|process||16 nm (0.016 μm, 1.6e-5 mm) +|