|Designer||University of Michigan, University of California, Cornell University, University of California|
|L1I Cache||4 KiB/core|
|L1D Cache||4 KiB/core|
Vanilla-5 is a custom RISC-V core microarchitecture designed specifically for the Celerity SoC. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego.
Vanilla-5 is a custom-designed RISC-V core designed by the Celerity SoC team for that chip. The core is a fully synthesized design that implements the RV32IM ISA (base as well as the integer and multiply extensions). Vanilla-5 was designed to take up very little silicon area. For that reason it uses an incredibly simple design - it's an in-order, single-issue, 5-stage design. Each core incorporates a 32-entry, 32b register file which is implemented using two 1R1W latch-based memory as well as a 4 KiB of private level 1 instruction cache and a private 4 KiB of private level 1 data cache. It's worth noting that the L1 caches on the Vanilla-5 cores behave more like scratchpads rather than tiered caches when they are integrated on Celerity since they are an explicitly managed part of a statically partitioned memory address.
The Vanilla-5 core is integrated into the Celerity SoC where it's used as part of a manycore array of 496 tiles. Each tile comprises a Vanilla-5 core and a router. The core is silicon-proven capable of up to 1.4 GHz.
The Vanilla-5 core is open source and can be found on https://bitbucket.org/taylor-bsg/bsg_manycore/src/master/v/vanilla_bean/
- 2019 Symposia on VLSI Technology and Circuits (VLSI 2019).
- IEEE Hot Chips 29 Symposium (HCS) 2017.
|designer||University of Michigan +, University of California + and Cornell University +|
|full page name||umich/microarchitectures/vanilla-5 +|
|instance of||microarchitecture +|
|instruction set architecture||RISC-V +|
|microarchitecture type||CPU +|
|pipeline stages||5 +|
|process||16 nm (0.016 μm, 1.6e-5 mm) +|