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Vanilla-5 - Microarchitectures

Edit Values
Vanilla-5 µarch
General Info
Arch TypeCPU
DesignerUniversity of Michigan, University of California, Cornell University, University of California
Process16 nm
Reg RenamingNo
ExtensionsInteger, Multiply
L1I Cache4 KiB/core
L1D Cache4 KiB/core

Vanilla-5 is a custom RISC-V core microarchitecture designed specifically for the Celerity SoC. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego.

Process technology[edit]

Vanilla-5 is integrated into the Celerity SoC which is fabricated on TSMC 16 nm process.


Vanilla-5 is a custom-designed RISC-V core designed by the Celerity SoC team for that chip. The core is a fully synthesized design that implements the RV32IM ISA (base as well as the integer and multiply extensions). Vanilla-5 was designed to take up very little silicon area. For that reason it uses an incredibly simple design - it's an in-order, single-issue, 5-stage design. Each core incorporates a 32-entry, 32b register file which is implemented using two 1R1W latch-based memory as well as a 4 KiB of private level 1 instruction cache and a private 4 KiB of private level 1 data cache. It's worth noting that the L1 caches on the Vanilla-5 cores behave more like scratchpads rather than tiered caches when they are integrated on Celerity since they are an explicitly managed part of a statically partitioned memory address.

The Vanilla-5 core is integrated into the Celerity SoC where it's used as part of a manycore array of 496 tiles. Each tile comprises a Vanilla-5 core and a router. The core is silicon-proven capable of up to 1.4 GHz.


vanilla-5 core.png

vanilla-5 (annotated).png


vanilla-5 routing.png


Type Area (µm²)  %
IMEM 6691 27.59
DMEM 6691 27.59
RF 2008 8.28
Core logic 2473 10.20
ALU 485 2.00
Div 412 1.70
Mult 301 1.24
Pipeline/other 1275 5.26
NoC 1881 7.76
Endpoint FIFO 303 1.25
Credit counter 23 0.09
Router 1555 6.41
Endcap/welltap 281 1.16
Filler 1635 6.74
Unutilized 2591 10.68
Total 24251 100.00

Source core[edit]

The Vanilla-5 core is open source and can be found on

See also[edit]


  • 2019 Symposia on VLSI Technology and Circuits (VLSI 2019).
  • IEEE Hot Chips 29 Symposium (HCS) 2017.
codenameVanilla-5 +
designerUniversity of Michigan +, University of California + and Cornell University +
full page nameumich/microarchitectures/vanilla-5 +
instance ofmicroarchitecture +
instruction set architectureRISC-V +
manufacturerTSMC +
microarchitecture typeCPU +
nameVanilla-5 +
pipeline stages5 +
process16 nm (0.016 μm, 1.6e-5 mm) +