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RISC-V (pronounced risk-five) is a free and open instruction set architecture standardized by the RISC-V Foundation that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as x86 and ARM, but rather to provide a foundation for emerging classes of processors and accelerators that require a base ISA on top of which additional functionality can be added.


RISC-V is a free and open ISA; no license is needed to be obtained and the use of the ISA royalty-free for anyone. RISC-V is designed to provide a foundation or a base architecture for companies and researchers who need it in order to be able to augment their own technology (e.g., customer accelerators, fixed function hardware, and other domain-specific additions) on top of it. RISC-V provides a base architecture (offered in 3 flavors of 32/64/128 bit) consisting of less than 50 instructions which is capable of running a full software stack including a full-fledged operating system. The core instructions are frozen and are guaranteed to never change. In addition to the core instructions, RISC-V provides a number of optional standard extensions that can be implemented or omitted depending on the designer goals. Other than the standard extensions RISC-V also reserves opcodes to be custom tailored by chip designers for their own applications.


Main article: RISC-V Foundation

Standardization is done by the RISC-V Foundation which was established specifically for this purpose as well as to promote and protect the ISA. The foundation can also elevate non-standard (e.g., DSEs) to standard extensions if determined robust and stable enough.


RISC-V is designed as a Base+Extension ISA whereby the architecture is broken down into a very minimal base architecture that is required in order to be able to get a full software stack including a full-fledged operating system and additional standard extensions can be implemented when additional functionality is desired.

There are three RISC-V base instruction called RV32I, RV64I, and RV128I. Those three variations only operate on integers and represent a 32-bit, 64-bit, and 128-bit address space and register widths (i.e., word size). All RISC-V implementations must include the base RV32I instructions. The two additional variations simply expand the RV32I register width and add a handful of additional data transfer instructions for working with wider words.