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Registers - RISC-V
< risc-v

RISC-V
Instruction Set Architecture
General
Base Variants(base)
Standard Extensions(all)
Topics

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RISC-V defines a set of registers that are part of the core ISA.

Overview[edit]

RISC-V base ISA consists of 32 general-purpose registers x1-x31 which hold integer values. The register x0 is hardwired to the constant 0. There is an additional user-visible program counter pc register which holds the address of the current instruction. RISC-V does not define a specific subroutine return address link register, but it does suggest that the standard software calling convention should use register x1 to store the return address on a call.

The width of those registers are defined by the RISC-V base variant used. That is, for RV32, the registers are 32 bits wide, for RV64, they are 64 bits, and for RV128, those registers are 128 bit wide.

Note that RISC-V defines a special ISA E for resource-constrained embedded applications which only defines 16 registers.


risc-v base integer regsiters.svg

Calling convention[edit]

In conventional RISC-V software, the stack grows downward with the stack pointer always being 16-byte aligned.

Register ABI Name Description Saver
x0 zero hardwired zero -
x1 ra return address Caller
x2 sp stack pointer Callee
x3 gp global pointer -
x4 tp thread pointer -
x5-7 t0-2 temporary registers Caller
x8 s0 / fp saved register / frame pointer Callee
x9 s1 saved register Callee
x10-11 a0-1 function arguments / return values Caller
x12-17 a2-7 function arguments Caller
x18-27 s2-11 saved registers Callee
x28-31 t3-6 temporary registers Caller