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Cortex-A9 - Microarchitectures - ARM
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Cortex-A9 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 3, 2007
Process40 nm
Instructions
ISAARMv7
Succession

Cortex-A9 is the successor to the Cortex-A8, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

The Cortex-A9 was later succeeded by four independent lines - high-performance (A15), mainstream performance (A12), high efficiency (A7), and ultra-low power (A5).

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a9 -mtune=cortex-a9
GCC -mcpu=cortex-a9 -mtune=cortex-a9
LLVM -mcpu=cortex-a9 -mtune=cortex-a9

One can specify NEON support using the -mfpu=neon option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON, under ARMv7, is not fully IEEE 754-compliant. It's possible to use -funsafe-math-optimizations to circumvent that behavior.

Architecture[edit]

Key changes from Cortex-A8[edit]

This list is incomplete; you can help by expanding it.

Licensees[edit]

Arm named the following companies as licensees.

codenameCortex-A9 +
designerARM Holdings +
first launchedOctober 3, 2007 +
full page namearm holdings/microarchitectures/cortex-a9 +
instance ofmicroarchitecture +
instruction set architectureARMv7 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A9 +
process40 nm (0.04 μm, 4.0e-5 mm) +