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Cortex-A12 - Microarchitectures - ARM
| Edit Values | |
| Cortex-A12 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | June 2, 2013 |
| Instructions | |
| ISA | ARMv7 |
| Succession | |
Cortex-A12 (codename Owl) is the successor to the Cortex-A9, a mid-range performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A12 was designed to be paired with the low-power Cortex-A7 in a big.LITTLE configuration.
Note that Arm withdrew the Cortex-A12 from their product offering in October 2014 due to having design and performance parameters very similar to its successor, the Cortex-A17.
Architecture[edit]
Key changes from Cortex-A9[edit]
- 28 nm process (from 40 nm)
- Longer pipeline (11, up from 9-12)
- Integer
- Hardware division support
- Hardware Fused Multiply-Accumulate
- VFPv4 (from VFPv3)
- NEONv2 (from NEON)
- Added LPAE support
This list is incomplete; you can help by expanding it.
Block Diagram[edit]
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This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy[edit]
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This section is empty; you can help add the missing info by editing this page. |
Facts about "Cortex-A12 - Microarchitectures - ARM"
| codename | Cortex-A12 + |
| designer | ARM Holdings + |
| first launched | June 2, 2013 + |
| full page name | arm holdings/microarchitectures/cortex-a12 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv7 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A12 + |