|Xeon Gold 5218|
|Introduction||March, 2019 (announced)|
March, 2019 (launched)
|Turbo Frequency||3,900 MHz (1 core)|
|Core Name||Cascade Lake SP|
|Word Size||64 bit|
|Max CPUs||4 (Multiprocessor)|
|Tcase||0 °C – 81 °C|
|TDTS||0 °C – 93 °C|
|Dimension||76.16 mm x 56.6 mm|
|Pitch||0.8585 mm x 0.9906 mm|
|Socket||LGA-3647 (Socket P-2016)|
Xeon Gold 5218 is a 64-bit 16-core x86 multi-socket high performance server microprocessor expected to be introduced by Intel in early 2019. This chip supports up to 4-way multiprocessing. The Gold 5218, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.3 GHz with a TDP of 105 W and a turbo boost frequency of up to 3.2 GHz, supports up ? GiB of hexa-channel DDR4-2400 ECC memory.
- Main article: Cascade Lake § Cache
[Edit/Modify Cache Info]
is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU
by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.
The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.
Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.
Note: All units are in kibibytes
|16x32 KiB||8-way set associative|| |
|16x32 KiB||8-way set associative||write-back|
| || ||16x1 MiB||16-way set associative||write-back|
| || ||16x1.375 MiB||11-way set associative||write-back|
[Edit/Modify Memory Info]
Integrated Memory Controller
|Max Mem||? GiB|
|Max Bandwidth||107.3 GiB/s|
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s