|Introduction||February 7, 2018 (announced)|
February 7, 2018 (launched)
|Turbo Frequency||3,000 MHz (1 core)|
|Bus type||DMI 3.0|
|Bus rate||4 × 8 GT/s|
|Core Name||Skylake DE|
|MCP||Yes (2 dies)|
|Word Size||64 bit|
|Max CPUs||1 (Uniprocessor)|
|Max Memory||512 GiB|
|Tcase||0 °C – 90 °C|
|Dimension||45 mm x 52.5 mm|
Xeon D-2142IT is a 64-bit 8-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 1.9 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 65 W. The D-2142IT supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of Skylake DE's Network Edge and Storage SKUs.
|| Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.
- Main article: Skylake § Cache
[Edit/Modify Cache Info]
is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU
by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.
The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.
Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.
Note: All units are in kibibytes
|8x32 KiB||8-way set associative|| |
|8x32 KiB||8-way set associative||write-back|
| || ||8x1 MiB||16-way set associative||write-back|
| || ||8x1.375 MiB||11-way set associative||write-back|
[Edit/Modify Memory Info]
Integrated Memory Controller
|Max Mem||512 GiB|
|Max Bandwidth||79.47 GiB/s|
Single 15.89 GiB/s
Double 31.78 GiB/s
Quad 63.57 GiB/s
|Physical Address (PAE)||46 bit|
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 PCIe lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.
- See also: Intel's CPU Frequency Behavior
[Modify Frequency Info]
|Mode||Base||Turbo Frequency/Active Cores|
|Normal||1,900 MHz||3,000 MHz||3,000 MHz||2,800 MHz||2,800 MHz||2,500 MHz||2,500 MHz||2,500 MHz||2,500 MHz|
|AVX2||2,800 MHz||2,800 MHz||2,600 MHz||2,600 MHz||2,400 MHz||2,400 MHz||2,400 MHz||2,400 MHz|
|AVX512||2,700 MHz||2,700 MHz||2,500 MHz||2,500 MHz||2,100 MHz||2,100 MHz||2,100 MHz||2,100 MHz|