From WikiChip
Xeon Gold 5215 - Intel
| Edit Values | |
| Xeon Gold 5215 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | 5215 |
| Part Number | CD8069504214002 |
| S-Spec | SRFBC QRG9 (QS) |
| Market | Server |
| Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
| Release Price | $1,221.00 (tray) |
| Shop | Amazon |
| General Specs | |
| Family | Xeon Gold |
| Series | 5200 |
| Locked | Yes |
| Frequency | 2,500 MHz |
| Turbo Frequency | 3,400 MHz (1 core) |
| Bus type | DMI 3.0 |
| Bus rate | 4 × 8 GT/s |
| Clock multiplier | 25 |
| CPUID | 0x50655 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Cascade Lake |
| Platform | Purley |
| Chipset | Lewisburg |
| Core Name | Cascade Lake SP |
| Core Family | 6 |
| Core Stepping | L0, L1 |
| Process | 14 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 10 |
| Threads | 20 |
| Max Memory | 1 TiB |
| Multiprocessing | |
| Max SMP | 4-Way (Multiprocessor) |
| Interconnect | UPI |
| Interconnect Links | 2 |
| Interconnect Rate | 10.4 GT/s |
| Electrical | |
| TDP | 85 W |
| Packaging | |
| Package | FCLGA-3647 (FCLGA) |
| Dimension | 76.16 mm × 56.6 mm |
| Pitch | 0.8585 mm × 0.9906 mm |
| Contacts | 3647 |
| Socket | Socket P, LGA-3647 |
| Succession | |
Xeon Gold 5215 is a 64-bit deca-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5215 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.5 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.4 GHz.
This model is offered with medium memory support (2 TiB, 5215M) and large memory support (4.5 TiB, 5215L).
Cache[edit]
- Main article: Cascade Lake § Cache
|
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Memory controller[edit]
|
Integrated Memory Controller
|
||||||||||||||
|
||||||||||||||
Expansions[edit]
Expansion Options |
|||||
|
|||||
Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
| Mode | Base | Turbo Frequency/Active Cores | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | ||
| Normal | 2,500MHz | 3,400MHz | 3,400MHz | 3,200MHz | 3,200MHz | 3,100MHz | 3,100MHz | 3,100MHz | 3,100MHz | 3,000MHz | 3,000MHz |
| AVX2 | 2,000MHz | 3,100MHz | 3,100MHz | 2,900MHz | 2,900MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,600MHz | 2,600MHz |
| AVX512 | 1,400MHz | 2,900MHz | 2,900MHz | 2,500MHz | 2,500MHz | 1,900MHz | 1,900MHz | 1,900MHz | 1,900MHz | 1,800MHz | 1,800MHz |
Facts about "Xeon Gold 5215 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5215 - Intel#pcie + |
| base frequency | 2,500 MHz (2.5 GHz, 2,500,000 kHz) + |
| bus links | 4 + |
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
| bus type | DMI 3.0 + |
| chipset | Lewisburg + |
| clock multiplier | 25 + |
| core count | 10 + |
| core family | 6 + |
| core name | Cascade Lake SP + |
| core stepping | L0 + and L1 + |
| cpuid | 0x50655 + |
| designer | Intel + |
| family | Xeon Gold + |
| first announced | April 2, 2019 + |
| first launched | April 2, 2019 + |
| full page name | intel/xeon gold/5215 + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
| has intel deep learning boost | true + |
| has intel enhanced speedstep technology | true + |
| has intel speed shift technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) + |
| ldate | April 2, 2019 + |
| main image | |
| manufacturer | Intel + |
| market segment | Server + |
| max cpu count | 4 + |
| max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
| max memory channels | 6 + |
| microarchitecture | Cascade Lake + |
| model number | 5215 + |
| name | Xeon Gold 5215 + |
| package | FCLGA-3647 + |
| part number | CD8069504214002 + |
| platform | Purley + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| release price | $ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) + |
| release price (tray) | $ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) + |
| s-spec | SRFBC + |
| s-spec (qs) | QRG9 + |
| series | 5200 + |
| smp interconnect | UPI + |
| smp interconnect links | 2 + |
| smp interconnect rate | 10.4 GT/s + |
| smp max ways | 4 + |
| socket | Socket P + and LGA-3647 + |
| supported memory type | DDR4-2666 + |
| tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
| technology | CMOS + |
| thread count | 20 + |
| turbo frequency (1 core) | 3,400 MHz (3.4 GHz, 3,400,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |