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Xeon Gold 5215 - Intel
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Xeon Gold 5215
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number5215
MarketServer
IntroductionDecember, 2018 (announced)
December, 2018 (launched)
General Specs
FamilyXeon Gold
Series5000
LockedYes
Frequency2,200 MHz
Turbo Frequency3,400 MHz (1 core)
Clock multiplier22
CPUID0x50655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores10
Threads20
Max CPUs4 (Multiprocessor)
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm x 56.6 mm
Pitch0.8585 mm x 0.9906 mm
Contact Count3647
SocketLGA-3647 (Socket P-2016)

Xeon Gold 5215 is a 64-bit deca-core x86 multi-socket high performance server microprocessor set to be introduced by Intel in late 2018. This chip supports up to 4-way multiprocessing. The Gold 5215, which is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm++ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.2 GHz with a TDP of ? W and a turbo boost frequency of up to 3.4 GHz, supports up ? GiB of hexa-channel DDR4-2400 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
0.625 MiB
655,360 B
6.103516e-4 GiB
L1I$320 KiB
0.313 MiB
327,680 B
3.051758e-4 GiB
10x32 KiB8-way set associative 
L1D$320 KiB
0.313 MiB
327,680 B
3.051758e-4 GiB
10x32 KiB8-way set associativewrite-back

L2$10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
  10x1 MiB16-way set associativewrite-back

L3$13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
  10x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

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Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem? GiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Double and Quad
AVX512VLAVX-512 Vector Length
AVX512VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 5215 - Intel#package +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipsetLewisburg +
clock multiplier22 +
core count10 +
core family6 +
core nameCascade Lake SP +
cpuid0x50655 +
designerIntel +
familyXeon Gold +
first announcedDecember 2018 +
first launchedDecember 2018 +
full page nameintel/xeon gold/5215 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size0.625 MiB (640 KiB, 655,360 B, 6.103516e-4 GiB) +
l1d$ description8-way set associative +
l1d$ size0.313 MiB (320 KiB, 327,680 B, 3.051758e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size0.313 MiB (320 KiB, 327,680 B, 3.051758e-4 GiB) +
l2$ description16-way set associative +
l2$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description11-way set associative +
l3$ size13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
ldate3000 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max cpu count4 +
max memory channels6 +
max pcie lanes48 +
microarchitectureCascade Lake +
model number5215 +
nameXeon Gold 5215 +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
series5000 +
socketSocket P-2016 +
supported memory typeDDR4-2400 +
technologyCMOS +
thread count20 +
turbo frequency (1 core)3,400 MHz (3.4 GHz, 3,400,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +