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K9 - Microarchitectures - AMD
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K9 µarch
General Info
Arch TypeCPU
Process65 nm

K9 was a planned microarchitecture developed by AMD as a successor to K8. The K9 codename might cover multiple projects at AMD. A deep pipeline design led by Mitch Alsup as Chief Architect, another one intended to bring massive parallelism[1] and finally, using K9 as a codename for dual-core K8.

The whole set of intended features and the exact reasons AMD cancelled K9 remain unknown.

Deep pipeline design[edit]

The design was led by Mitch Alsup as Chief Architect and attempted to directly compete with Intel NetBurst. It featured a deep pipeline and an advanced trace cache.

According to Alsup, it was designed to be close to 95% of original K8 IPC but reach 5GHz frequency in a 35 nm process. At the time of cancellation most of the logic was running in SPICE at 5GHz and majority of the layout was done.

The K9 pipeline was dual-quad issue. It was described by Alsup as: "K9 fetched 8 instructions every other cycle and made 2 branch predictions associated with 3 next fetch addresses every other cycle. K9 issued 4 instructions per cycle and took 2 cycles to issue a fetch width."

Reportedly, the design was cancelled due to leakage current problems amplified by necessity to embrace the multi-core era. K9's DDR2 SDRAM controller was later used in K8 Rev F and its northbridge technology got put in K8 Rev G.


  1. Anand Lal Shimpi, Why is Barcelona late? - AMD - The Road Ahead, Retrieved on December 1, 2018
codenameK9 +
designerAMD +
full page nameamd/microarchitectures/k9 +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerAMD +
microarchitecture typeCPU +
nameK9 +
process65 nm (0.065 μm, 6.5e-5 mm) +