|Manufacturer||VLSI Technology, Sanyo|
|L1 Cache||4 KiB/core|
64-way set associative
- 1 History
- 2 Process Technology
- 3 Architecture
- 4 Overview
- 5 Die
- 6 All ARM3 Chips
- 7 References
- See also: ARM's History
The ARM3 builds on the success of the ARM2 with higher performance through the introduction of on-die cache but without any major changes to the core itself. The ARM3 was designed by a team of four engineers in nine months and was introduced in 1989. The ARM3 can operate at up to 25 MHz with a peak performance of 25 MIPS and a sustainable performance of 12 MIPS.
- See also: 1.5 µm process
The major goal of the ARM3 was to improve performance. A target of three times the performance of the ARM2 was set. In order to support a faster microprocessor, the system would have to use faster DRAM which would negatively impact the overall cost. Instead, the design team opted to integrating cache.
- Goal 3x the performance
- Integrated cache
- Integrated clock generator
- Integrated control logic
- Integrated co-processor interface
New ARM3 instructions:
SWP- Swap word memory-register, Atomic (uninterruptible)
- L1 Cache (unified)
- 4 KiB, 64-way set associative
- 16 B line size
- Write-through policy
- Per core
- L1 Cache (unified)
- System DRAM
- Up to 64 MiB
The ARM3's control logic is a state machine implemented as three PLAs. Layout was generated automatically using EDA tools using Psuedo nMOS logic in order to save on space, albeit at the slight expense of static power dissipation.
- Main article: ARM2 Pipeline
ARM3's pipeline is identical to the ARM2.
To increase performance, Acorn needed to increase the clock speed. This was not possible without leaving commodity DRAM for higher speed and more expensive DRAM. The alternative approach Acorn went with is an intermediate cache on-die. The ARM3 has two clock inputs, one fast one for the internal cache and one slower one for the external memory accesses. The two inputs are entirely independent allowing the system to optimize for both (fast cache and slower memory) at the same time.
Acorn introduced cache with the ARM3. This meant that most instructions are now coming from the on-chip cache instead of system memory. The way the coprocessor was originally designed in the ARM2 meant that the coprocessor could simply access its instructions from memory. This was no longer compatible with the new design. Acorn solved this problem by making the coprocessor lag behind exactly one cycle. Instructions that are identified as being coprocessor instructions are broadcasted off-chip on the following cycle. This was done using the processor's 32-bit data port along with timing and handshaking signals.
The ARM3's cache consists of a RAM and 4 tag CAM banks of 64 22-bit entries each for 64-way set associative. The choice of a 4-way split was entirely driven by the great reduction in power dissipation, at the cost of negligible performance (due to only 1/4th of the total CAM being enabled at any given time). Each CAM entry refers to one line of data in the RAM. Each line consists of four 32-bit words (i.e., 128 bit lines) with the low-order address bits being used for the select lines.
On a miss, a pseudo-random number generator is used to select an entry to evict and replace. On replacement a full line of four words is fetched from memory to minimize consecutive read operations. The cache uses a write-through update policy to ensure consistency. On a hit the appropriate line address are generated to be retrieved by the RAM.
The CAM consists of individual cells of six-transistor storage elements with a three-transistor comparators. The cell size was reported by Acorn to be 31.2 µm x 36.8 µm (1148.16 µm²) on a 1.5 µm process. The entry matching and address encoding logic uses dynamic logic in order to reduce power. The RAM is arranged in array of 128 x 256 cells with a 3-bit column elect, producing a 32-bit output. The SRAM cells used were standard 6T SRAM cells measuring 19.6 µm x 28.4 µm. Self-timing logic is used to disable the 32 sense amplifiers when the data becomes valid in order to reduce power.
- 12 MHz, 1 W
- 1.5 µm DLM CMOS
- 8.72 mm x 9.95 mm
- 86.764 mm² die size
- 309,656 transistors
- 206,454 SRAM
- 62,973 CAM
- 40,229 logic
- 119 signal pins
- 41 power/ground pins
All ARM3 Chips
|List of ARM3-based Processors|
|Model||Process||Launched||Frequency||Power Dissipation||Max Memory|
0.02 GHz, 25 MHz
- Thomas, A. R. P., et al. "A 2nd Generation 32b RISC Processor with 4KByte Cache." Solid-State Circuits Conference, 1989. ESSCIRC'89. Proceedings of the 15th European. IEEE, 1989.
|core count||1 +|
|designer||Acorn Computers +|
|first launched||1989 +|
|full page name||acorn/microarchitectures/arm3 +|
|instance of||microarchitecture +|
|instruction set architecture||ARMv2a +|
|manufacturer||VLSI Technology + and Sanyo +|
|microarchitecture type||CPU +|
|pipeline stages||3 +|
|process||1,500 nm (1.5 μm, 0.0015 mm) +|